DIRECTORY CD,CDIO,Core,CoreClasses,CoreDirectory,-- CoreOps, -- CoreProperties,IO,PWCore,Rope,SC,RTTestUtil;SCTestCoreTiny: CEDAR PROGRAMIMPORTS CDIO, CoreDirectory, -- CoreOps, -- CoreProperties, PWCore, RTTestUtil -- , SC --EXPORTS RTTestUtil =BEGINCreateCore: PUBLIC PROC [libName: Rope.ROPE] RETURNS [Core.CellType] =BEGINscCutSet: ATOM _ $SCPlacableElement;			-- leaf of the SC layout systemcoreLibrary: CoreDirectory.Library _ CoreDirectory.CreateLibrary[];libDesign: CD.Design _ CDIO.ReadDesign[libName, NIL, CDIO.GetWorkingDirectory[]];feedthruWires: Core.Wire _ RTTestUtil.CreateWire[LIST["InOut", "Vdd", "Gnd"]];feedthru: Core.CellType _ RTTestUtil.CreateRecordCell["feedthru", feedthruWires, feedthruWires, NIL];vddWires: Core.Wire _ RTTestUtil.CreateWire[LIST["Vdd", "Gnd"]];vdd: Core.CellType _ RTTestUtil.CreateRecordCell["vdd", vddWires, vddWires, NIL];gndWires: Core.Wire _ RTTestUtil.CreateWire[LIST["Vdd", "Gnd"]];gnd: Core.CellType _ RTTestUtil.CreateRecordCell["gnd", gndWires, gndWires, NIL];nandWires: Core.Wire _ RTTestUtil.CreateWire[LIST["InA", "InB", "Out", "Vdd", "Gnd"]];nand: Core.CellType _ RTTestUtil.CreateRecordCell["NAND", nandWires, nandWires, NIL];invWires: Core.Wire _ RTTestUtil.CreateWire[LIST["In", "Out", "Vdd", "Gnd"]];inverter: Core.CellType _ RTTestUtil.CreateRecordCell["Inverter", invWires, invWires, NIL];pubWires: Core.Wire _ RTTestUtil.CreateWire[LIST["InA", "Out", "Vdd", "Gnd"]];privateWires: Core.Wire _ RTTestUtil.CreateWire[LIST["NOut"]];internWires: Core.Wire _ RTTestUtil.UnionWire[pubWires, privateWires];nandInst: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["InA", "Vdd", "NOut", "Vdd", "Gnd"], nand, "nandInst", internWires];invInst: CoreClasses.CellInstance _ RTTestUtil.CreateInstance[LIST["NOut", "Out", "Vdd", "Gnd"], inverter, "invInst", internWires];SCTest: Core.CellType _ RTTestUtil.CreateRecordCell["SCTest", pubWires, internWires, LIST[nandInst, invInst]];-- CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "InA"], SC.sideProp, SC.bottomSideValue];-- CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Out"], SC.sideProp, SC.leftSideValue];-- CoreProperties.PutCellInstanceProp[nandInst, SC.rowProp, NEW[INT _ 1]];-- CoreProperties.PutCellInstanceProp[invInst, SC.rowProp, NEW[INT _ 2]];[] _ CoreDirectory.RegisterLibrary[coreLibrary,  libName];[] _ CoreDirectory.Insert[coreLibrary,  "NAND", nand, TRUE];[] _ CoreDirectory.Insert[coreLibrary,  "Inverter", inverter, TRUE];[] _ CoreDirectory.Insert[coreLibrary,  "feedthru", feedthru, TRUE];[] _ CoreDirectory.Insert[coreLibrary,  "vdd", vdd, TRUE];[] _ CoreDirectory.Insert[coreLibrary,  "gnd", gnd, TRUE];PWCore.SetGet[nand, libDesign];PWCore.SetGet[inverter, libDesign];PWCore.SetGet[feedthru, libDesign];PWCore.SetGet[vdd, libDesign];PWCore.SetGet[gnd, libDesign];CoreProperties.PutCellTypeProp[on: nand, prop: scCutSet, value: $T];CoreProperties.PutCellTypeProp[on: inverter, prop: scCutSet, value: $T];RETURN [SCTest];END;END.   È  SCTestCoreTiny.mesaCopyright c 1985 by Xerox Corporation.  All rights reserved.Frank Bowers December 19, 1985 10:36:54 am PSTBryan Preas March 24, 1986 5:11:33 pm PSTCreate a Core design Ê¤  ˜ Jšœ™šœ
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