Common Types
RopeList: TYPE = LIST OF Rope.ROPE;
Layer: TYPE = CD.Layer;
Rect: TYPE = CD.Rect;
RefRect: TYPE = REF Rect;
Pos: TYPE = CD.Position;
Number: TYPE = CD.Number;
SideOrNone: TYPE = DABasics.SideOrNone;
Side: TYPE = DABasics.Side;
Direction: TYPE = DABasics.Direction;
Errors
Error: ERROR [errorType: ErrorType ← callingError, explanation: Rope.ROPE ← NIL];
Signal: SIGNAL [signalType: ErrorType ← callingError, explanation: Rope.ROPE ← NIL];
ErrorType: TYPE = {programmingError, callingError, noResource, other};
Design Rules
DesignRules: TYPE = REF DesignRulesRec;
DesignRulesRec:
TYPE =
RECORD[
horizLayer, vertLayer: Rope.ROPE,
rowParms, sideParms: Route.DesignRulesParameters,
rowRules, sideRules: Route.DesignRules
];
CreateDesignRules:
PROC [technologyKey:
ATOM, horizLayer, vertLayer: Rope.
ROPE, rowDirection: Direction]
RETURNS [designRules: DesignRules];
Define the standard cell design rules. technologyKey values must correspond to one of the ChipNDale technologies. horizLayer, vertLayer should be "poly", "metal" or "metal2".
Standard Cell Handles and Results
Handle: TYPE = REF HandleRec;
HandleRec:
TYPE =
RECORD [
name: Rope.ROPE ← NIL,
coreCellType: Core.CellType ← NIL,
rules: DesignRules ← NIL,
parms: PRIVATE REF ANY ← NIL,
structureData: PRIVATE REF ANY ← NIL,
layoutData: PRIVATE REF ANY ← NIL];
Result: TYPE = REF ResultRec;
ResultRec:
TYPE =
RECORD[
handle: Handle,
object: CD.Object,
rect: Rect ← [0, 0, 0, 0],
polyLength, metalLength, metal2Length, polyToMetal, metalToMetal2: NAT ← 0,
numIncompletes: NAT ← 0,
incompleteNets: RopeList ← NIL];
CreateHandle:
PROC [cellType: Core.CellType, flattenCellType: RTCoreUtil.FlattenCellTypeProc, libName: Rope.
ROPE ←
NIL, designRules: DesignRules, name: Rope.
ROPE ←
NIL, decoration: CoreGeometry.Decoration]
RETURNS [handle: Handle];
Create a StdCellHandle. The StdCellHandle definition includes the design rules (conductor and via widths and spacings) for the routing channels as well as the circuit structure definition.
Properties
numRows:
ATOM;
Used to specify the number of rows for a standard cell assembly. Should be a property on Core cellType being laid out
sideProp, bottomSideValue, rightSideValue, topSideValue, leftSideValue, noSideValue:
ATOM;
Used to specify the side on which a public pin is to be placed. sideProp with (mumble)Value should be a property/value on a public wire
rowProp:
ATOM;
Used to specify the row on which a logic cell is to be placed. rowProp and and integer row number should be a property/value on a locig cell insatance
positionProp:
ATOM;
Used to specify the position of a logic within a row or of an public pin on a side. May be used on public wire or a logic cell instance.
usePublicPositionsProp:
ATOM;
Used to specify the position of a public in the schematic is to be retained int the layout
leftPowerProp, rightPowerProp:
ATOM;
Used to specify the side on which power busses are to be placed. May be used on 0, 1 or 2 public wires.
investmentProp, veryLongValue, longValue, mediumValue, shortValue, veryShortValue:
ATOM;
Used to specify indirectly the investment to make in placement.
t0SA, maxTStepSA, lambdaSA, tableSizeSA, limitSA:
ATOM;
Used to specify DIRECTLY the investment to make in placement.
bottomMaxExits, rightMaxExits, topMaxExits, leftMaxExits:
ATOM;
Used to specify the maximum number or exits on a side.
bottomExitSpacing, rightExitSpacing, topExitSpacing, leftExitSpacing:
ATOM;
Used to specify the HINT for publics spacing on a side.
interestingProperties: RTCoreUtil.PropertyKeys;
Used to specify all the properties that aer interesting to SC
widthFactorProp:
ATOM;
specifies the allowed length of the longest row compared to the minimun distance longest row
handleAtom:
ATOM;
for internal use only
Standard Cell Optimization and Construction
The following operations are available for a standard cell design.
InitialPlace:
PROC [handle: Handle, numRows:
NAT ← 0];
Determine an initial placement for the instances.
PosImprove:
PROC [handle: Handle, maxCycles:
INT ← 5];
Improve the positions of instances within rows.
FTImprove:
PROC [handle: Handle, maxCycles:
INT ← 5];
Improve the positions of the feedthrus within rows.
PosImproveWL:
PROC [handle: Handle, maxCycles:
INT ← 5];
Improve the positions of instances within rows using wire lenght as figure of merit.
OrientImprove:
PROC [handle: Handle, maxCycles:
INT ← 5];
Improve the orientation of instances.
OrientImproveWL:
PROC [handle: Handle, maxCycles:
INT ← 5];
Improve the orientation of instances using wire lenght as figure of merit.
HowLongToWork: TYPE = {veryLong, long, medium, short, veryShort, noInvestmentProp};
SAParms:
TYPE =
RECORD [
t0: REAL ← 100000.0, maxTStep: REAL ← 0.75, lambda: REAL ← 0.7, tableSize, limit: INT ← 200];
SAInitialResult:
TYPE =
RECORD [
minScore, maxScore, minDelta, maxDelta, avgDelta, standardDeviation: REAL ← 0.0,
numTotal, numDecrease, numIncrease, numNeutral: INT ← 0];
SAInitialPlace:
PROC [handle: Handle, widthFactor:
REAL ← 1.1, seed:
INT ← 0]
RETURNS [initialResult: SAInitialResult];
Initialize for simulated annealing improvement.
SAGetParms:
PROC [handle: Handle, initialResult: SAInitialResult, cellType: Core.CellType]
RETURNS [saParms: SAParms];
determine parameters for simulated placement.
SAPlaceImprove:
PROC [handle: Handle, saParms: SAParms, widthFactor:
REAL ← 1.1, seed:
INT ← 0];
Improve the placement for the instances (in pairs) by simulated annealing.
SAPlaceImproveM:
PROC [handle: Handle, saParms: SAParms, widthFactor:
REAL ← 1.1, seed:
INT ← 0];
Improve the placement for the instances (one at a time) by simulated annealing.
PlaceImprove:
PROC [handle: Handle, maxCycles:
INT ← 0];
Improve the placement for the instances by exhaustive search.
GlobalRoute:
PROC [handle: Handle];
Determine strategic paths for the wiring that must cross cell rows.
DetailRoute:
PROC [handle: Handle]
RETURNS [result: Result];
Determine actual wiring paths. Create a ChipNDale object and include the placement and routing in the object.
The cellType to layout is a record cellType containing elements from MSI; the layout proc flattens the Core description and calls the standard cell placer and router.
StandardCellLayout: PWCore.LayoutProc;
StandardCellDecorate: PWCore.DecorateProc;
Puts as property on public wires their side
StandardCellAttibutes: PUBLIC PWCore.AttributesProc; -- [cellType: Core.CellType]