DIRECTORY CD, CDSequencer, CDSequencerExtras, Core, CoreCDUser, CoreOps, DesignRules, Drc, DrcCmosb, IO, PW, PWCore, Rope, TerminalIO;DAUserDrcCmd: CEDAR PROGRAMIMPORTS CDSequencerExtras, CoreOps, CoreCDUser, DesignRules, Drc, DrcCmosb, IO, PW, PWCore, TerminalIO= BEGINGetRules: PROC [design: CD.Design] RETURNS [drcAtom: ATOM, techD: Drc.Tech] = {rules: DesignRules.Rules;drcAtom _ DesignRules.FetchRulesID[design];IF drcAtom = NIL THEN drcAtom _ $VTI;rules _ DesignRules.GetRuleSet[drcAtom ! DesignRules.DesignRuleError => CONTINUE];IF rules = NIL THEN {TerminalIO.PutF["Unknown design rule key: %g\n", IO.atom[drcAtom]];drcAtom _ $VTI;rules _ DesignRules.GetRuleSet[drcAtom];};techD _ DrcCmosb.NewTechnology[DrcCmosb.cMosBcompleteKey, rules];};ExtractAndDrc: PROC [comm: CDSequencer.Command] = {DoOne: CoreCDUser.EachRootCellTypeProc ~ {quantity: INT _ 0;name: IO.ROPE _ CoreOps.GetCellTypeName[root];ect: Core.CellType;obj: CD.Object;TerminalIO.PutF["Generating and extracting layout for %g.\n", IO.rope[name]];[layout: obj, extractedCT: ect] _ PWCore.LayoutInfo[root];TerminalIO.PutF["Layout generation and extraction done for %g.\n", IO.rope[name]];TerminalIO.PutF["DRC checking %g.\n", IO.rope[name]];quantity _ Drc.CheckDesignRules[cell: ect, external: CoreOps.CopyWire [ect.public], tech: techD, viaFlatness: viaFlatness, stopFlag: NEW [BOOL _ FALSE], lap: NEW [CARDINAL], currentCell: NEW [Rope.ROPE], layout: PWCore.extractMode.decoration];IF quantity>0 THEN {[] _ PW.Draw[obj]; TerminalIO.PutRope["*** "]};TerminalIO.PutF["Finished %g Drc of %g: %g violation%g. %g\n",IO.atom[drcAtom],IO.rope[name],IO.int[quantity],IO.rope[IF quantity#1 THEN "s" ELSE ""],IO.rope[IF viaFlatness THEN "Via flatness checked." ELSE ""]];};lastBadOb: CD.Object _ NIL;viaFlatness: BOOL _ SELECT comm.key FROM$LayoutNDrcViasOn	=>	TRUE,$LayoutNDrcViasOff	=>	FALSE,$LayoutNDRC			=>	(TerminalIO.RequestSelection[header:		"Check Via Flatness",choice:		LIST["Check via flatness", "Don't check via flatness"], headerDoc:	"Set up flat data structures to check via flatness",choiceDoc:	LIST["Not reasonable for large (>3 level) hierarchies", ""],default:		1] # 2),ENDCASE	=> ERROR;drcAtom: ATOM; techD: Drc.Tech;[drcAtom, techD] _ GetRules[comm.design];TerminalIO.PutF["Using %g design rules.\n", IO.atom[drcAtom]];[] _ CoreCDUser.EnumerateSelectedCellTypes[comm.design, DoOne];};CDSequencerExtras.RegisterCommand[key: $LayoutNDRC, proc: ExtractAndDrc, queue: doQueue];CDSequencerExtras.RegisterCommand[key: $LayoutNDrcViasOn, proc: ExtractAndDrc, queue: doQueue];CDSequencerExtras.RegisterCommand[key: $LayoutNDrcViasOff, proc: ExtractAndDrc, queue: doQueue];END.   ٹ  DAUserDrcCmd.mesaCopyright س 1987, 1988 by Xerox Corporation.  All rights reserved.Last Edited by: Louis Monier January 7, 1987 8:15:20 pm PSTLast Edited by: Christian Jacobi, January 7, 1987 11:41:28 am PSTgbb January 22, 1988 11:29:03 am PSTJean-Marc Frailong December 8, 1987 9:55:49 pm PSTBarth, April 2, 1987 11:58:37 am PSTBertrand Serlet September 15, 1987 8:12:20 pm PDT ‌ت  –"cedar" styleک codeڑœ™KڑœB™BKڑœ8دk™;Kڑœ>‌™AK™$K™2Kڑœ!‌™$Kڑœ1™1K™ —ڑ‌	œ‌œY‌œ‌œک†Kک —•StartOfExpansion[]ڑدnœ‌œ‌کKڑ‌œE‌œ‌œکfKڑœ‌کKک —ڑ
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