All dimensions are in
l (currently 1 micrometer).
$Get, $GetAndFlatten (Bertrand Serlet et al.)
PWCoreSourceDesign:
CD.Design;
-- mandatory
Looks for foo.mask in specified design. Same design is the Sisyph variable design. Publics of the extracted CellType must correspond [by full name] to the original public. GetAndFlatten flattens the layout, so that corresponding transistors inter-cells are fused.
More doc: PWCore.mesa
$Abut, $AbutX, $AbutY (Bertrand Serlet et al.)
On recordCell CellTypes only. Sorts the instances according to the Sisyph decoration. The individual cells may be of varying width, but the pitch must be the same. For Abut, the schematics indicates whether concatenation should be in the x or y direction.
More doc: PWCore.mesa
$ArrayX, $ArrayY (Bertrand Serlet et al.)
On sequenceCell CellTypes only. Similar to abuts.
More doc: PWCore.mesa
$FlipX, $FlipY, $Rot90, $Rot180, $Rot270 (Bertrand Serlet et al.)
The cellType must be a RecordCell with a unique instance. Orientations based on ChipNDale.
More doc: PWCore.mesa
$Extend (Don Curry)
The cellType must be a RecordCell with a unique instance.
Bottom, Right, Top, Left: INT; -- amount of extension; default is 0
More doc: CoreRouteDoc.tioga
$ChangeLayers (Don Curry)
The cellType must be a RecordCell with a unique instance. The layout object returned is made up of the layout of the subcell surrounded by routing cells which change the routing layer between Metal and Metal2 and bus one signal per side (typically Vdd or Gnd) into one or two external pin(s) per side.
One property may be placed on the bussed schematic wires.
w: INT; -- specifies a larger than default bus width.
More doc: CoreRouteDoc.tioga
$ChannelRoute (Louis Monier, Bryan Preas)
The cellType must be a RecordCell with exactly two instances.
The schematic is parsed to determine whether the channel should be horizontal or vertical; the wires which have pins at the edge (perpendicular to the channel) and between the projections of the 2 instances will become channel exits. Thoses wires can be structured, but then only atomic wires are taken into account.
Trunk: ATOM or ROPE; -- defaults to Metal
Branch: ATOM or ROPE; -- defaults to Metal2
JustifyTopOrRight: REF; -- if non-NIL, layouts should be top-justified (for a channel in X, and resp. right-justified for a channel in Y). Default (NIL) means bottom or left justification.
DesignRules: ATOM; -- Defaults to $cmosB
TotalWidth: INT; -- the total width of the channel plus both objects
One property may be placed on the schematic wires:
w: INT; -- channel trunk wire width; default is defined by design rules
More doc: CoreRouteDoc.tioga
$Stack (Don Curry)
$Stack is a general purpose, one-dimensional layout operator. It is used to specify routing of a variable number of cells that form a stack in either the horizontal or vertical direction. (Note that the horizontal and vertical directions refer to cells. When the cells are stacked horizontally, the channels are vertical. Conversely, when the cells are stacked vertically, the channels are horizontal.) The $Stack operator abuts any cells that are specifically abutted in the schematic and creates channels between all other subcells.
Trunk: ATOM or ROPE; -- see ChannelRoute
Branch: ATOM or ROPE; -- see ChannelRoute
JustifyTopOrRight: REF; -- see ChannelRoute
HorizontalStack: REF; -- specifies when non-NIL a horizontal stack. This is used only in the degenerate case of a stack containing just one subcell. It essentially determines which ends of the subcell can have channel routes.
And one property may be placed on the schematic wires:
w: INT; -- specifies a larger than default channel trunk wire width.
More doc: CoreRouteDoc.tioga
$SC, $SCRemote (Christian Lecocq, Bryan Preas)
Produces a Standard Cells block. Flattens the cellType until its finds a cell having a Layout property. This means in particular that no block inside should carry Layout: $SC. In generating layout for a given schematic the $SC generator retains the geometry of the public wire sequence of the schematic so that a public wire that crosses the left edge of the interestRect in the schematic will touch the left edge of the interestRect for the corresponding layout.
SC uses a in-house placer, SCRemote uses Timberwolf, a placer running on Sun workstations.
numRows: INT; -- number of rows; default is to make the block square
UsePublicPositions: BOOL; -- if TRUE, the position of a public in the schematic is to be retained in the layout
More doc: Bryan's left cerebral hemisphere; I have a map to his office. You can also browse in SC25.df to find command files that direct the placement to a particular Sun workstation.
$SCRoute (Christian Lecocq, Bryan Preas)
Similar to SCRemote, but starts from a placement and just performs the routing. Quite mysterious I must say.
More doc: none.
$Padframe (Louis Monier, Bryan Preas)
Expects four sides and an inner. Position of these five objects should be totally non-ambiguous.
VerticalMetal: ROPE; -- "metal" or "metal2"
outerWidth: INT; -- size of the external channel; defaulted to 90
powerWidth: INT; -- size of the power region; defaulted to 200
innerDX: INT; -- horizontal displacement of the inner; defaulted to 0
innerDY: INT; -- vertical displacement of the inner; defaulted to 0
More doc: PadFramesDoc.tioga. For an example, see /Indigo/Dragon/BIC2/BIC.dale.
$DataPath (Don Curry)
Not out yet.
$PLAGen (Don Curry)
Not out yet.