Create the tester for the specified CT within the specified design. The following properties of the CT determine simulation details:
Tests : <LIST OF ROPE> -- name of TestProcs to be used, default is LIST["Logic Test"] (the standard TestProc)
RecordDeltas: BOOL -- if FALSE, do not record anything during simulation; if TRUE, record simulation events (for plotting mostly). Defaults to TRUE
RecordSteps: BOOL -- if FALSE, record values only at Evals boundaries; if TRUE, record all modifications of wires. Defaults to TRUE.
CutSet: <CoreFlat.CutSet> -- specifies the cutset used for simulation. Default is NIL, i.e. transistor level simulation. Convenient standard values are found in Logic.fast, Logic.macro, etc...