a single wire (as opposed to a group of wires)

 describes CellTypes used in the Core data structure whose CellClass does not provide a Recast Proc to express the decomposition of the CellType into a simpler, logically equivalent manner. There is exactly one CellClass that could provide a Recast Proc to express its decomposition in a simpler, logically equivalent form but does not do so. This is the RecordCellClass. The other CellTypes whose CellClasses do not provide a Recast Proc are either atomic, for example the transistor CellType, or have an undefined decomposition.

 a technique used to conserve area on a chip by coalescing the contacts between layers

 connection between the poly and diffusion layers of a chip made to avoid creating a transistor

 a switch in which some analog tricks are used to keep the electrical potential at 2.5 volts (rather than at 0 volts) so that the amount of current needed to get to 5 volts is less

 a rectangular routing region with terminals along its edges. Horizontal channels have terminals along their top and bottom edges. Vertical channels have terminals along their right and left edges. The objective of channel routing is to electrically connect all the nets using a minimum width channel.

 large printout of the mask-level description of an integrated circuit

 Caltech Intermediate Form, a standard machine readable form for representing integrated system layouts

 a compiler that takes a description of the topology of a cell and creates a mask to be used as a blueprint in fabricating the circuit. Because the compiler tries to create as compact a mask as possible, it is known as a compactor.

 circuit primitives to be used in creating integrated circuits

 Conform as used in the DATools documentation and interfaces describes a function to map public to actual wires such that every actual has some public that corresponds to it and furthermore, for every actual subwire its number of children is the same as the number of children of the corresponding public subwire.

 Here is a formal definition:

 Conform(a, p) {  f: p* b a* such that

 A conforms to p iff there exists a function f which maps every subwire of p into some subwire of a, and in particular maps p into a, and for every subwire p' of p, f(p') has the same number of children as p' and for every index i [0..p') f(p'[i]) is the f(p')child[i].

 In writing the above, the following unusual notations have been used.

 w* means wire w and all its subwires

 |w| means the number of children of w

 w[i] means the i'th child of w 

 a condition that occurs when the interconnection wiring is too dense so that there is some undesirable interaction among the net. Conestion may a global measurement, for instance, all the nets that cross a cut line, or a local measure such as track density with a routing channel.

 A circuit is core-limited if the area needed to generate the circuit logic is greater than the perimeter needed to generate the circuit's signals. (c.f. pad-limited)

 describes the structuring mechanism used to take a collection of cell types of various classes and bind them together. See [DATools]<DATools7.0>Core>CoreClasses.mesa for more details.

 A design is the object created by the user. It may represent one or many circuits. Every design is in a particular technology (CMos-B, NMos) and consists of some geometry and a Directory.

 converts the approximate routes created by global routing into exact routes (c.f. routing)

 Electronic Design Interchange Format. EDIF is gaining industry acceptance as a standard means of exchanging design information from foundry-to-designer and from designer-to foundry.

 pins that have common internal connections

 The placement of standard cells in a VLSI circuit sometimes requires connections between cells that are separated by an intervening row. When this occurs a cell containing that signal is created in the intervening row. This cell is called a feedthrough.

 A term used to describe the process of placing the functional units of either an integrated circuits or a system. In integrated circuit placement the floorplanning process tends toward a bottom-up physical approach, while in system design floorplanning tends to be top-down and functional. Flooringplanning can be used as a tool to focus on the trade-offs that must be made on a number of metrics including area, speed, power, testability to create an optimal design.

 signals that are inputs to a cell that have equivalent effect on the signals produced at the output pins. For example, the two inputs to a NAND gate are functionally equivalent or the address pins of a random access memory cell. Placement is often improved by modifying the assignment of nets among functionally equivalent pins.

 a physical design style that starts with a standard cell library including and predefined placement of the standard cells. A circuit is designed by specifying the connections between the standard cells. Because the standard cells are stationary, the areas available for routing are fixed. An area may become congested when the connections assigned to the area require more routing resources than are available.

 maps logical gates from a structural description of a circuit onto functionally equivalent physical gates within a component. In actuality, logically equivalent circuits are not constrained to be gates, so that the term gate assignment is a misnomer. The gate assignment problem was first formulated in PCB design where the circuits were gates and the term remains in common use.

 resolves net lists into approximate routes that consist of horizontal and vertical line segments (c.f. routing)

 In the DATools world, boxes with public wires that represent either a schematic or a piece of Cedar code.

 in ChipNDale, import means to make a reference to the imported design. If objects are changed in the imported design, and the design that references them is re-loaded, the changes made are propagated to our importing design. (c.f. include)

 in ChipNDale, include means to take some objects from one design and literally copy them into another design. No links are established between the objects in question. If the original objects change, the design that was created using these objects will not change. (c.f. import)

 the connections among the signal sets of an integrated circuit

 defines the public wire of a schematic. also determines where electrical connections may be made when a schematic is used directly within another schematic

 the black ouline displayed when a cell is selected. This definition is not 100% exact. The InterestRect is not the bounding box of the geometry, there are other xxxRect for that. Its important properties are:

 1.  PW uses the InterestRect to abut objects.

 2.  You can set it interactively with S-Middle, and it becomes then independent of the geometry of the object. Once you set it, it stays, even if you edit the cell. If you don't set it, the default is (almost) the bounding box, but if you make minor edits to the cell, it might change and give you trouble when abuting cells.

 the abstraction of the physical surface (carrier) on which circuit elements are placed. Models of the physical surface fall into two categories: geometric and topological. p. 92, chapter 4 for more info.

 Level-Sensitive Scan Design. A termed coined at IBM to refer to a particular way of implementing the scan path. (See the definition for scan path below.)

 a template containing the precise images to be used in patterning silicon wafers

 in the placement of cells and macro-cells of an integrated circuit, a circuit is described as non-slicing if it cannot be hierarchically divided by single horizontal or vertical lines into two subparts until all the cells are separated. Programming languages can easily represent slicing structures by binary trees. Non-slicing structures are much more difficult to represent.

 A VLSI circuit is pad-limited if the perimeter dictated by the circuit's signals (pins) is greater than the area required by the circuit logic used to create the signals. Thus, pad-limited circuits typically have some amount of unused space between the circuit pads and the core of the circuit.

 A circuit that is pad-limited, thus having some unused silicon area will have a higher yield than a circuit of the same area that is not pad-limited. (c.f. core-limited)

 Printed Circuit Board

 A pin is an area chosen by the cell designer where a connection is to occur. the terminals of a component that are to be connected during the layout process. Pins define the are at which the internal circuitry of a cell connects to the external circuitry. In printed circuit board technology, the pin corresponds to a physical entity and is the only way to form a connection at the herarchical boundry. In IC technology, pins are a modeling convenience which allows the details of the internal circuitry of the devices to be abstracted away.

 process of assigning nets among functionally equivalent pins of a component. This process seeks to reduce wiring length, reduce crossovers or congestion.

 the process of positioning the components of an integrated circuit. The major focus in placement is on minimizing the length of interconnection wiring because this minimum length translates into the minimum time required for propagation of signals, and thus into the best performance for the completed circuit. The placement function considers only those properties that are important to the electrical and physical interface with the rest of the circuit and layout surface. These are: physical size and shape of the object, the location in three dimensions (geometric coordinates and the physical interconnection layer) of the signal pins and power supply pins. (Preas, Placement, Assignment and Floorplanning, p. 86) (c.f. routing)

 involves either transformations on or transformations into information used in manufacture of physical systems

 converts the representation of the children of a cell type into a representation which is closer to the root of the partially ordered set

 the process of making all the connections between all the cells of an integrated circuit or the components of a printed circuit board. For integrated circuits, routing is often divided into a global phase where approximate routes are defined and a detailed phase where exact routes are chosen. (c.f. placement)

 the area of an integrated circuit that is used to make all the connections between various cells. For circuits designed using standard cells, this area is about 60% of the overall circuit area.

 a design strategy for testing VLSI circuits that allows the internal function of a circuit to be observed and controlled. Signals are sent to a couple of test pins to force the circuit to function in test mode. When in this mode, the integrated circuit connects some or all of its flip-flops into a single shift register so that the bits in those elements can be shifted out, examined, perhaps changed, and shifted back in. The design must be synchronous for this testing strategy to work. The reason a scan path design strategy is not universally used is that making the flip-flops function both normally and as a shift register consumes silicon real estate and can also make the flip-flops somewhat slower.

 a diagram drawn using icons, wires, expressions, and other schematics that describes the functionality of an integrated circuit

 a style of gate array that does not have predefined routing areas

 a list of the terminals or pins on the components that are to be connected in the layout process

 in the placement of cells and macro-cells of an integrated circuit, a circuit structure is described as slicing if can be hierarchically sliced by single horizontal or vertical lines into two subparts until all the cells are separated. Each horizontal or vertical cutline used corresponds to one routing channel and the channels are routed in the reverse order of slicing.

 Simulation Program Integrated Circuit Emphasis

 an algorithm used for standard cell placement that is analogous to the annealing process during crystallization. A parameter called the temperature is defined that represents the overall cost (wiring length) of the current configuration. Changes to the current configuration are made at random. Changes that improve upon the current configuration are accepted. Changes that do not improve upon the current configuration are accepted with a probability of exp(-DE/T) where DE is the increase in cost and T is the temperature. Thus, at high temperature almost all moves are accepted, while at low temperature only moves that improve upon the current configuration are likely to be accepted.

 The system is started with a high temperature so that almost all changes are accepted. A gradual cooling schedule, developed by statistical analysis for the standard cell placement problem, lowers the temperature until the system converges upon the least-cost solution.

 

 portions of nets

 a four-sided channel that is formed at the intersection of two or more channel routing regions. Terminals are located on all four sides of the rectangular region.

 the horizontal and vertical grid lines of a channel

 an electrical switch which is either on (conducting) or off (not conducting) current. In the fabrication process for integrated circuits, a transistor is created any place polysilicon crosses diffusion.

 drivers that can do one of three things: drive the output high, drive the output low, or appear as a high impedance to output

 volume allocation map

 in CMOS technology, contacts between metal1 and metal2 layers.

 because the posts that implement the pins have a fixed height, each pin can generally have only 3 connections.