Documentation: PadFrameDoc.tioga

Created by: Bertrand Serlet

Maintained by: Bertrand Serlet <Serlet.pa>

Documentation: BooleDoc.tioga

Keywords: Boolean Algebra, Boolean expressions, Disjunctive Normal Form, PLA, DCVS, Cascode, Static, FSM, Finite State Machines, Automatas

Abstract: Boole (also called Alps) is a layout generator which accepts a set of boolean equations, much like PLA generators do. It makes use of an original tree-structured representation of arbitrary boolean expressions. This representation is usually more compact than the classic disjunctive form, is suitable for fast symbolic manipulation, and maps naturally into silicon. Boole produces static CMOS layout using the cascode switch style. In the same package, there is a starting point for finite state machines.

Created by: Bertrand Serlet

Maintained by: Bertrand Serlet <Serlet.pa>

Documentation: BringDAToolsDoc.tioga

Keywords: Design automation, Bringover, DATools, DF Files, DAToolsAdministration

Commands: BringDATools

Abstract: BringDATools is a command that brings over all the released DATools software in much less time that traditional bringovers.

Documentation: cd25.tioga, substitute25.tioga

Commands: CDOpen, CDRead, ChipNDale, CDGenerate

Documentation: ChipNDaleIntroduction.tioga, ChipNDaleDoc.tioga, ChipNDaleToolsDoc.tioga, CDCrib.tioga, ChipNDaleLabelsAndTextsDoc.tioga, ChipNDale-RegistrationDoc.tioga, ChipNDaleProgramsDoc.tioga, ChipNDaleMessages1987.tioga, ChipNDaleMessages1986.tioga, ChipNDaleMessages1985.tioga, ChipNDaleMessages1984.tioga, ChipNDaleMessages1983.tioga, dale.tioga, CDOldDocuments.tioga

Documentation: LogicDoc.Tioga, StdCellsCmosBDoc.tioga, DynabusPadsDoc.tioga

Created by: Bertrand Serlet

Maintained by: Maintainers of CellLibraries

Documentation: CellLibrariesGenDoc.Tioga

Keywords: CellLibraries, .corelib Files

Abstract: CellLibrariesGen is a package precomputing information which is expensive to recompute. This information is capture in .corelib files belonging to the CellLibraries package. Therefore this module is reserved for maintainors of CellLibraries, and not for general public.

Created by: Don Curry

Maintained by: Don Curry <Curry.pa>

Documentation: CheckDesignDoc.tioga

Keywords: Finishing check, verification

Commands: CheckDesign

Abstract: CheckDesign is meant to be a finishing check for designs and libraries. It applies both Static and Mint to the source and applies Lichen, Mint and Dracula to the layout.

Created by: Christian Le Cocq, with pieces from previous work of Frank Bowers, Jim Gasbarro, Christian Jacobi, Kimr, Ed McCreight, Martin Newell, Bertrand Serlet...

Maintained by: Christian Le Cocq <LeCocq.pa>

Documentation: CifCDConvertDoc.tioga

Keywords: CIF, Conversion

Abstract: Two packages, CDToCif and CifToCD, to allow integration of tools from other environments (which usually allow for CIF input & output) in the Cedar DATools world.

Created by: Christian Le Cocq

Maintained by: Christian Le Cocq <LeCocq.pa>

Documentation: CifParserDoc.tioga

Keywords: CIF, parser.

Abstract: The CIF parser provides a parser of the Caltech Intermediate Form description language, a format widely used to carry the geometrical description of the integrated circuits.

Created by: Bertrand Serlet

Maintained by: Serlet <Serlet.pa>

Documentation: CombinatorialDoc.tioga

Keywords: Core, Boolean Algebra, Boolean Expressions

Abstract: Combinatorial defines the notion of combinatorial cells. A syntax for boolean expressions and the corresponding parser are defined, as well as generic operations for manipulating combinatorial cells.

Created by: Bruce Wagar

Maintained by: Bertrand Serlet <Serlet.pa>, Louis Monier <Monier.pa>

Documentation: ConnectivityCheckerDoc.tioga

Keywords: Connectivity Checker, PWCore, Rectangle Intersection, Bags

Commands: CheckConnectivity

Abstract: Verifies that each wire has all its geometry in one piece. In particular, checks that fusion by name (or fusion by source) did not introduce disconnections.

Created by: Bertrand Serlet, Mike Spreitzer and Rick Barth

Maintained by: Barth <Barth.pa>, Serlet <Serlet.pa>, Spreitzer <Spreitzer.pa>

Documentation: CoreDoc.tioga, CoreDescription.tioga

Keywords: ChipNDale, Design Automation, Tools Integration

Abstract: Core is a common set of interfaces for exchanging information between different DA tools. It is also used to capture the designer's intents at a high level.

Created by: Bertrand Serlet, Louis Monier, Bryan Preas, Don Curry

Maintained by: Bertrand Serlet <Serlet.pa>, Louis Monier <Monier.pa>, Don Curry <Curry.pa>

Documentation: CoreRouteDoc.tioga

Keywords: Router, PatchWork, PWCore, Tools Integration

Abstract: CoreRoute allows interfacing purely geometric routers to the world of structure. CoreRoute does not route in itself but calls routers within the framework define by PWCore.

Created by: Giordano Beretta

Maintained by: DAToolsImplementors^.pa

Documentation: CoreViewDoc.Tioga

Keywords: Core, Debugging, Design Automation Tools, Extraction, Illustration, Layout Visualization, Technology Independence, Viewers

Abstract: CoreView visualizes the geometry in a Core data structure. Two options are available. With the first option a Core cell is recursively traversed and its geometry is painted into a viewer. The same non-linear RGB model as in Nectarine is used, hence the Cedar color map should be used. The second option simply creates an empty viewer, into which rectangles can be added incrementally. Viewers created with the second option are monochrome, every rectangle is labelled. This second option is intended for debugging packages based on Core.

Created by: John Ousterhout

Maintained by: Le Cocq <LeCocq.pa>

Documentation: CrystalDoc.tioga

Keywords: VLSI, Layout, Timing Analysis

Abstract: Crystal is a time-critical path finder for layout of VLSIs.

Documentation: DataPathNotes.tioga

Created by: Bertrand Serlet and Mike Spreitzer

Maintained by: Bertrand Serlet <Serlet.pa>, Mike Spreitzer <Spreitzer.pa>

Documentation: DAToolsAdministrationDoc.tioga, DAToolsCatalog.tioga

Keywords: DATools, Software Management, Release, DF Files, Version Maps, Changes Tracking, Rules, Locks, User Profile, MakeDo, BringDATools

Abstract: This document describes the DATools software management rules for design aids implementors. It is mostly an edited versage of a message from Mike Spreitzer. For retrieving DA software, see BringDAToolsDoc.

Created by: Christain LeCocq and Lissy Bland

Maintained by: Lissy Bland <Bland.pa>

Documentation: DAToolsExamplesDoc.tioga

Keywords: Cedar example

Abstract: This is a simple Cedar program that uses some of the important interfaces from the DATools. The program registers a new command with ChipNDale whose purpose is to write the result of Sisyph's circuit extraction to a file. The default filename is cellName.coreList.

Created by: Bryan Preas, Christian Jacobi, and many others

Maintained by: Bryan Preas <Preas.pa>

Documentation: DAToolsFormsDoc.tioga

Keywords: form, document, message, style, abbreviation, DF, interface, release, CedarChest

Abstract: DAToolsForms.df describes a number of forms in used in the DATools context, in addition to Forms.df.

Created by: Bertrand Serlet

Maintained by: Serlet <Serlet.pa>, Barth <Barth.pa>, Monier <Monier.pa>

Documentation: DAToolsIntroductionDoc.tioga, DAToolsGlossary.tioga, DATools7.0ReleaseMessage.tioga, DAUserDoc.tioga, LayoutAtomsDoc.tioga, OnePageCDCommandSummary.tioga

Keywords: Design automation, Core, ChipNDale, DATools, Schematics, Simulation, Catalog, BringDATools, Conversion, Static, Design Rules Check, TextOps, EditTool

Abstract: DAUser is a repository for commands, documentation or programs which are at the crossroad of different tools. For retrieving DA software, see BringDAToolsDoc.

Created by: Christian Le Cocq

Maintained by: Christian Le Cocq <LeCocq.pa>

Documentation: DraculaOpsDoc.tioga

Keywords: VLSI, DRC, Unix.

Commands: DraculaDRC

Abstract: DraculaOps provides a simple way to use the Dracula DRC in the Unix environment from Cedar.

Created by: Pradeep Sindhu as NewCoreClasses

Maintained by: Christian Le Cocq <LeCocq.pa>

Documentation: ElectricalCoreClassesDoc.tioga

Keywords: Circuit Simulation, Schematics Extraction

Abstract: ElectricalCoreClasses contains the definitions of the basic elements used in the electrical description of the circuits. It more or less follows the description understood by Spice.

Created by: Bertrand Serlet

Maintained by: Serlet <Serlet.pa>, Frailong <Frailong.pa>, Sindhu <Sindhu.pa>

Documentation: ExtractDoc.tioga, SisyphDoc.tioga, ToBeChanged.tioga

Keywords: Layout Extractor, Schematics Extractor, Extraction, Technology Independent Extraction, Core, ChipNDale, Schematics, Wire Icons, Icons, Visual Programming, Schematics, Geometry Decorations

Abstract: Extract is a package grouping the extraction engine [Sinix], the layout extractor and the schematics extractor [Sisyph]. It also defines the important notion of decorated Core [CoreGeometry].

Commands: Mux8

Created by: Giordano Beretta

Maintained by: DAToolsImplementors^.pa

Documentation: GenistaDoc.Tioga

Keywords: Core, Design Rule Checking, Layout Verification, Design Automation Tools, Technology Independence

Commands: DrcCdCMOSb, DrcRepeal, DrcEmpty, DrcRedo, DrcStatus, TestGenista

Abstract: Genista is the Grandson of Spinifex. It is a partially hierarchical design rule checker that enumerates a Core design and uses the ChipNDale geometry with which it is decorated.

Created by: Sweetsun Chen

Maintained by: Sweetsun Chen <SChen.pa>

Documentation: GraphDoc.tioga

Keywords: Graph, Controller, Thyme, Post Processor.

Commands: Graph, Waves

Abstract: Graph is a tool for creating or editing line graphs (x-y charts) manually or programmably. Many convenient functionalities are supported. The first section below contains tutorial steps to help users get familiar with the package easily.

Created by: Don Curry

Maintained by: Don Curry

Documentation: IcPackDoc.tioga

Keywords: IC Package, Bonding Diagram

Commands: BuildIcPack, GenExpertPinLists, GenCoordPinList, GenMTSPinList

Abstract: IcPack provides a way to capture the last level of device specification in the design of a VSLI circuit, that of the package bonding diagram. It does this by building a scale model representing the layout pads for a device and including this model in a copy of a package object. Besides being used as the graphical bonding specification, the output of this package can be used to provide interface references for the tester and board level software.

Created by: Jim Gasbarro

Maintained by: Jim <Gasbarro.pa>

Documentation: IMSTesterDoc.tioga

Keywords: IMS, VLSI testing, Probe station

Abstract: This document describes the resources and configuration of the IMS chip tester.

Commands: IMSLink

Created by: Christian Le Cocq

Maintained by: Le Cocq <LeCocq.pa>

Documentation: MintDoc.tioga

Keywords: Circuit Simulation, Graph Display

Abstract: Mint is a program that simulates a Core data structure extracted from a layout. It offers also a static electrical checker, and a timing analyzer.

Created by: Jean-Marc Frailong

Maintained by: Jean-Marc Frailong <Frailong.pa>

Documentation: MTSVectorDoc.tioga, MTSHardDoc.tioga

Keywords: Dragon, VLSI, Hybrid, Test

Abstract: This package permits to generate and run test files for the MTS tester. Stimuli are captured from a transistor-level Rosemary simulation.

Created by: Giordano Bruno Beretta

Maintained by: DAToolsImplementors^.pa

Documentation: NectarineDoc.Tioga, NectarineTune.tioga

Keywords: ChipNDale, ChipNSil, Design Automation Tools, Documentation, Document Processing, Graph Display, Illustration, Imaging, Interpress, Layout Printing, PD Files, Peach Expansion, Peach Printing, Printing, Schematics Printing, Technology Independence, Tioga Illustration

Commands: Nectarine, NCount, NectarineField, NOldColors, NQuery, NReadColors, NRedo, NWriteColors, PrintDesignOnVersatec

Abstract: The ultimate layout and schematics documentation and printing system. Creates Interpress masters and does with them anything you might dream of: stuffs into Tioga documents, prints on Interpress servers and Peach servers, in black and white or in colour, expanding on the printer server or on a special expansion server. Once three buttons are bugged to answer three orthogonal questions (what, where, how often), all the magic happens with the single press of a button. The Interpress masters can be further manipulated with Gargoyle.

Commands: PLAOpsCompress

Created by: Bertrand Serlet

Maintained by: Serlet <Serlet.pa>

Documentation: PWDoc.tioga, OldPatchWorkDoc.tioga

Keywords: ChipNDale, Design Automation, Layout Generation, Layout Assembly, Silicon Assembly

Abstract: PW offers a layer on top of ChipNDale in order to facilitate layout generation. It is the result of a long evolution from Louis Monier's PatchWork (cf OldPatchWorkDoc.tioga). PW also contains a tiny demo of ChipNDale and of the package.

Created by: Bertrand Serlet, Louis Monier

Maintained by: Serlet <Serlet.pa>

Documentation: PWCoreDoc.tioga

Keywords: Comparator, Core, ChipNDale, PatchWork, Extraction, Sinix, Decorations, Interface Geometry

Abstract: PatchWork (= PWCore) is the general framework for connecting CD layout to Core. The Core structure either comes from schematics, or by a piece of code. In both cases, this Core data structure is decorated with some properties, which permit the construction of the corresponding layout. When the layout is constructed, publics of cells having layout are decorated with the interface geometry, to allow for routing. An interface check is made at decoration time.

Created by: Mike Spreitzer <Spreitzer.pa>, Bertrand Serlet <Serlet.pa>

Maintained by: Mike Spreitzer <Spreitzer.pa>, Bertrand Serlet <Serlet.pa>

Documentation: PWCoreLichenDoc.Tioga

Keywords: PWCore, Hierarchical Comparison, Structural Comparison, Comparison, Core, ChipNDale

Abstract: PWCoreLichen hierarchically compares two Core descriptions of a circuit for structural equivalence. The hierarchies don't have to be exactly the same, and the structures don't have to be absolutely identical. It works in the context of PWCore. One of the Core descriptions is called the `source', and the other is called the `extracted', because it is intended to be extracted from the ChipNDale description fabricated by PWCore according to the source description. PWCoreLichen's checking is not complete; there is a tool, called the ConnectivityChecker, that complements PWCoreLichen. There is a ChipNDale command interface to PWCoreLichen, as well as a Cedar language interface.

Created by: Louis Monier

Maintained by: Serlet <Serlet.pa>, Monier <Monier.pa>

Documentation: PWPLADoc.tioga

Abstract: PWPLA is a PLA generator. It uses a library of cells, a set of user-defined parameters including a truth-table, and generates PLAs with the help of PatchWork. It can be used interactively from ChipnDale. Its procedural interface make it also easy to call from any user program.

Created by: Bertrand Serlet

Maintained by: Serlet <Serlet.pa>

Documentation: RawExtractDoc.tioga

Keywords: Layout Extractor, Raw Extraction, HighLight, PadFrame

Abstract: RawExtract provides an extraction mode that takes into account overlap. Utilities for extraction of entire chips or for highlighting (even in standard mode) are also found in this module.

Created by: Don Curry

Maintained by: Don Curry <Curry.pa>

Documentation: REFBitDoc.tioga

Keywords: REF BitArray

Commands: REFBitFormat

Abstract: When designing and simulating hardware, it's sometimes useful to deal with instances of arbitray Cedar TYPEs as if they were arrays of bits.

Created by: Rick Barth

Maintained by: Barth <Barth.pa>

Documentation: RosemaryDoc.tioga, RosemaryExample.tioga, RosemaryTemplate.tioga, RoseThoughts.tioga

Keywords: Simulation

Abstract: Rosemary is a simulator.

Documentation: RouteAttributes.tioga

Created by: Giordano Beretta

Maintained by: DAToolsImplementors^.pa

Documentation: SaguaroDoc.Tioga, ECADVTIRulesTemplate.tioga

Keywords: ChipNDale, Core, Extraction, Extractor, Geometry Decorations, Layout, Technology Independent Extraction, Transistor

Abstract: Prepares the data about transistors that is needed by the extractor.

Documentation: SCThingsToDo.tioga

Created by: Rick Barth

Maintained by: Barth <Barth.pa>

Documentation: ScaldDoc.tioga

Keywords: scald, file format

Abstract: Scald writes scald format files.

Created by: Christian Le Cocq

Maintained by: Christian Le Cocq <LeCocq.pa>

Documentation: SpiceOpsDoc.tioga, SpiceUserGuide.tioga

Keywords: Circuit Simulation, Schematics Extraction,

Commands: SpiceOps

Abstract: SpiceOps provides (as much as possible) simple ways to use the Spice Circuit simulator on the Vax in the Unix environment from our DATools in the Cedar environment.

Created by: Rick Barth

Maintained by: Barth <Barth.pa>

Documentation: StaticDoc.tioga

Keywords: design automation, static checking

Abstract: Static checks that some interesting invariants hold.

Created by: Don Curry

Maintained by: Don Curry <Curry.pa>

Documentation: StretchCMosBDoc.tioga

Keywords: Stretch, Extend

Abstract: Stretches selected CMosB Object by creating a new object with 'tabs' added on all four sides. User may specify stretch width in lambda and whether only routing layers (poly, metal, metal2), all conductive layers or all CMosB layers are to be stretched.

Documentation: IntHashTableThreadedDoc.tioga

Created by: Neil Welhelm, modified by SChen.pa

Maintained by: LeCocq.pa & DAToolsImplementors^.pa

Documentation: CoreThymeDoc.tioga, ThymeDoc.tioga, ThymeManual.tioga

Keywords: Circuit Simulation, Graph, Timing Diagrams.

Commands: Thyme

Abstract: Thyme is a circuit simulator originally written in the Alto environment in 1982, and ported to Cedar in 1984. This documentation only dicusses the special features of its Cedar version.

Created by: Christian Le Cocq

Maintained by: Christian Le Cocq <LeCocq.PA>

Documentation: WriteCapaDoc.tioga

Keywords: Capacitance, Layout, Core Wire

Abstract: WriteCapa writes the capacitances of the layout wires as properties on the CoreWires