1.3 V Memory Contoller on two sheets (as background) 1.7 P Crossram (see Brian) 1.7 V Ram from Logic 2.8 M Ugly.sch 2.8 M Better.sch 2.8 M LatchIfValid.sch 3.1 V Memory Controller source sch. 3.2 M FSM from MapCache 3.3 V Large Data path from Memory Contoller (for panning) 3.4 V Pads from Memory Contoller (check with JMF) 3.5 Block of SC 3.5 M bonding diagram 3.5 M oracle 3.5 M Spice test circuit (see Ed Richley) 5.3 M MapCacheTop.icon 5.4 V MapCacheTop.sch 5.5 M ram2Cells.sch in LogicRam2 5.6 M ram2Cell.sch and ram2Cell.mask in LogicRam2 5.8 M Layout of ram2Cells.sch 5.8 Layout of array, array+I/O, complete ram at same scale 5.10 V Layout of fifo, +ram1, +ram2, +SC, complete inner at same scale 5.12 V Layout of inner, +pads, complete map cache at same scale 5.14 Assortment of sch. with get, abut, rotate, flip 5.16 M Two ram cells layout with arrow showing one abutted to another lDACTapeList.tioga Louis Monier April 14, 1988 10:50:01 pm PDT Plots (V=Versatec, M=MtFuji, P=Photo) ΚΩ˜šœ™Icode™+—J™Ihead2™%J˜5J˜J˜J˜Jšœ˜Jšœ˜Jšœ˜J˜J˜$Jšœ˜Jšœ:˜:Jšœ2˜2Jšœ˜Jšœ˜Jšœ ˜ Jšœ*˜*J˜Jšœ˜Jšœ˜Jšœ!˜!Jšœ2˜2Jšœ˜Jšœ<˜