CRProcsImpl.mesa
Copyright © 1985 by Xerox Corporation. All rights reserved.
Barth, March 16, 1987 4:50:27 pm PST
DIRECTORY
Basics, BitOps, Core, CoreClasses, CoreCreate, CoreOps, CRProcs, CD, PWCore, Sisyph, SSI;
CRProcsImpl:
CEDAR
PROGRAM
IMPORTS Basics, BitOps, CoreCreate, CoreOps, PWCore, Sisyph, SSI
EXPORTS CRProcs =
BEGIN OPEN CoreCreate;
InitContext:
PUBLIC
PROC [cx: Sisyph.Context] = {
selectBits: INT = 8;
log2SelectBits: INT = BitOps.Log2[selectBits];
addressDecoderBits: INT = CRProcs.addressBits-log2SelectBits;
andPlaneBits: INT = addressDecoderBits-1;
Sisyph.Store[cx, "dataBits", NEW[INT ← CRProcs.dataBits]];
Sisyph.Store[cx, "addressBits", NEW[INT ← CRProcs.addressBits]];
Sisyph.Store[cx, "selectBits", NEW[INT ← selectBits]];
Sisyph.Store[cx, "rowQuads", NEW[INT ← CRProcs.rowQuads]];
Sisyph.Store[cx, "log2SelectBits", NEW[INT ← log2SelectBits]];
Sisyph.Store[cx, "addressDecoderBits", NEW[INT ← addressDecoderBits]];
Sisyph.Store[cx, "andPlaneBits", NEW[INT ← andPlaneBits]];
};
DecoderLogicDriver:
PUBLIC
PROC [cx: Sisyph.Context]
RETURNS [ct: CellType] = {
select: NAT ← Sisyph.FetchInt[cx, "selectBits"].value;
log2Select: NAT ← Sisyph.FetchInt[cx, "log2SelectBits"].value;
invert8: CellType ← SSI.Inverter[];
and: CellType ← SSI.And[i: log2Select];
instances: CoreClasses.CellInstances ← NIL;
FOR adrBit:
INT
IN [0 .. log2Select)
DO
instances ←
CONS [
Instance[
invert8,
["Input", Index["LowAddressB", adrBit]],
["nOutput", Index["nLowAddressB", adrBit]]
],
instances];
ENDLOOP;
FOR sel:
INT
IN [0 .. select)
DO
bind: LIST OF WR ← NIL;
FOR adrBit:
INT
DECREASING
IN [0 .. log2Select)
DO
bind ←
CONS [
Index[
IF Basics.BITAND[Basics.BITSHIFT[sel, adrBit-log2Select+1], 1]#0 THEN "LowAddressB" ELSE "nLowAddressB",
adrBit],
bind];
ENDLOOP;
instances ←
CONS [
Instance[
and,
["Input", WireList[bind]],
["Output", Index["Select", sel]]
],
instances];
ENDLOOP;
ct ← Cell[
name: "DecoderLogicDriver",
public: Wires["Vdd", "Gnd", "AdrBit", "nAdrBit", Seq["LowAddressB", log2Select], Seq["Select", select]],
onlyInternal: Wires[Seq["nLowAddressB", log2Select]],
instances: instances
];
PWCore.SetGet[ct, Sisyph.GetDesign[cx]];
};
DecoderAndPlane:
PUBLIC
PROC [cx: Sisyph.Context]
RETURNS [ct: CellType] = {
DecoderRow:
PROC [row:
NAT]
RETURNS [ct: CellType] = {
AdrBit: Wire ← Seq["AdrBit", andPlaneBits];
nAdrBit: Wire ← Seq["nAdrBit", andPlaneBits];
nDecode: Wire ← CoreOps.CreateWire[name: "nDecode"];
Gnd: Wire ← CoreOps.CreateWire[name: "Gnd"];
SeriesInternal: Wire ← Seq["SeriesInternal", andPlaneBits-1];
instances: CoreClasses.CellInstances ← NIL;
FOR adrBit:
NAT
DECREASING IN [0..andPlaneBits)
DO
instances ←
CONS [
Instance[
IF BitOps.EBFW[row, adrBit, andPlaneBits] THEN dec1
ELSE dec0,
["AdrBit", AdrBit[adrBit]],
["nAdrBit", nAdrBit[adrBit]],
["SeriesTop", IF adrBit=andPlaneBits-1 THEN nDecode ELSE SeriesInternal[adrBit]],
["SeriesBottom", IF adrBit=0 THEN Gnd ELSE SeriesInternal[adrBit-1]]],
instances];
ENDLOOP;
ct ← Cell[
public: Wires["Vdd", Gnd, AdrBit, nAdrBit, nDecode],
onlyInternal: Wires[SeriesInternal],
instances: instances];
PWCore.SetAbutX[ct];
};
design: CD.Design ← Sisyph.GetDesign[cx];
rowQuads: NAT ← Sisyph.FetchInt[cx, "rowQuads"].value;
andPlaneBits: NAT ← Sisyph.FetchInt[cx, "andPlaneBits"].value;
dec0: Core.CellType ← Sisyph.ExtractSchematicByName[ "DecoderZero.sch", cx];
dec1: Core.CellType ← Sisyph.ExtractSchematicByName[ "DecoderOne.sch", cx];
instances: CoreClasses.CellInstances ← NIL;
nDecode: Wire ← Seq["nDecode", 2*rowQuads];
PWCore.SetGet[dec0, design];
PWCore.SetGet[dec1, design];
FOR rowQ:
NAT
IN [0..rowQuads)
DO
instances ←
CONS [
Instance[
DecoderRow[2*rowQ],
["nDecode", nDecode[2*rowQ]]],
instances];
instances ←
CONS [
Instance[
PWCore.RotateCellType[DecoderRow[2*rowQ+1], $FlipY],
["nDecode", nDecode[2*rowQ+1]]],
instances];
ENDLOOP;
ct ← Cell[
name: "DecoderAndPlane",
public: Wires["Vdd", "Gnd", Seq["AdrBit", andPlaneBits], Seq["nAdrBit", andPlaneBits], nDecode],
instances: instances];
PWCore.SetAbutY[ct];
};
DataBufferMux:
PUBLIC
PROC [cx: Sisyph.Context]
RETURNS [ct: CellType] = {
SelectRow:
PROC [row:
NAT]
RETURNS [ct: CellType] = {
Bit: Wire ← Seq["Bit", selectBits];
nBit: Wire ← Seq["nBit", selectBits];
Select: Wire ← CoreOps.CreateWire[name: "Select"];
VSelect: Wire ← Seq["VSelect", row];
instances: CoreClasses.CellInstances ← NIL;
FOR col:
NAT
DECREASING IN [0..selectBits)
DO
subCell: CellType ←
SELECT
TRUE
FROM
row<col => BitSelNoPoly,
row=col => BitSelContact,
row>col => BitSelPoly,
ENDCASE => ERROR;
instances ←
CONS [
Instance[
subCell,
["Bit", Bit[col]],
["nBit", nBit[col]],
["Select", Select],
IF subCell=BitSelPoly THEN ["VSelect", VSelect[col]] ELSE []],
instances];
ENDLOOP;
ct ← Cell[
public: Wires[Bit, nBit, Select, IF VSelect.size>0 THEN VSelect ELSE NIL],
instances: instances];
PWCore.SetAbutX[ct];
};
selectBits: NAT ← Sisyph.FetchInt[cx, "selectBits"].value;
design: CD.Design ← Sisyph.GetDesign[cx];
BitSelNoPoly: CellType ← Cell[
name: "BitSelNoPoly",
public: Wires["Select", "nBit", "Bit"],
instances: NIL];
BitSelContact: CellType ← Cell[
name: "BitSelContact",
public: Wires["Select", "nBit", "Bit"],
instances: NIL];
BitSelPoly: CellType ← Cell[
name: "BitSelPoly",
public: Wires["VSelect", "Select", "nBit", "Bit"],
instances: NIL];
Select: Wire ← Seq["Select", selectBits];
Bit: Wire ← Seq["Bit", selectBits];
nBit: Wire ← Seq["nBit", selectBits];
instances: CoreClasses.CellInstances ← NIL;
PWCore.SetGet[BitSelNoPoly, design];
PWCore.SetGet[BitSelContact, design];
PWCore.SetGet[BitSelPoly, design];
FOR row:
NAT
DECREASING IN [0..selectBits)
DO
rowCell: CellType ← SelectRow[row];
publicV: Wire ← FindWire[rowCell.public, "VSelect"];
pas: LIST OF PA ← CONS[["Select", Select[row]], NIL];
FOR col:
NAT
IN [0..row)
DO
pas ← CONS[[publicV[col], Select[col]], pas];
ENDLOOP;
instances ← CONS[InstanceList[rowCell, pas], instances];
ENDLOOP;
ct ← Cell[
name: "DataBufferMux",
public: Wires[Select, Bit, nBit],
instances: instances];
PWCore.SetAbutY[ct];
};
END.