<> <> <> <> <> DIRECTORY CD, Core, CoreClasses, CoreFlat, CoreGeometry, DABasics, RefTab, Rope, Route, SymTab; <> <<>> CoreRoute: CEDAR DEFINITIONS = BEGIN Side: TYPE = CoreGeometry.Side; CellType: TYPE = Core.CellType; Wire: TYPE = Core.Wire; <> <> <> LabelInternal: PROC [internal: Core.WireSeq, wire: Wire] RETURNS [Route.Label]; <> <<>> LabelFlatWire: PROC [root: CellType, flatWire: CoreFlat.FlatWireRec] RETURNS [Route.Label]; <> <<>> LabelBrokenNet: PROC [label: Route.Label, number: NAT] RETURNS [Route.Label]; <> <> <> <<>> WirePin: TYPE = RECORD [wire: Wire, min, max: INT, layer: CD.Layer]; WirePins: TYPE = LIST OF WirePin; FilteredCellTypeLayoutPins: PROC [cellType: CellType, side: Side] RETURNS [pins: WirePins]; <> <> <> <> <<>> FilteredInstanceLayoutPins: PROC [inst: CoreClasses.CellInstance, side: Side] RETURNS [pins: WirePins]; <> <> <<>> OrderedAtomicSchWires: PROC [cellType: CellType, side: Side, min: INT _ FIRST[INT], max: INT _ LAST[INT]] RETURNS [wires: Core.Wires]; <> <> <<>> FlushLayPinCache: PROC [cellType: CellType]; FlushSchPinCache: PROC [cellType: CellType]; <> <> <<- The cellType is a record cell for which all flat CT have layout.>> <<- The layout is only made of routing cells or of layout obtained through PWCore.Layout, or any structuration (cells, abuts, etc...) of those.>> <<- All sublayout obtained through PWCore.Layout can be sorted, all flat CT having layout can be sorted, and there is a one to one correspondance between those lists.>> <<- All nodes of all routing cells have a $SignalName property that labels that node.>> <<- A function mapping internal wires to labels is passed as argument.>> <<>> CompareFlatCTProc: TYPE = PROC [root: CellType, flatCT1, flatCT2: CoreFlat.FlatCellTypeRec] RETURNS [BOOL]; <> <> <<>> CompareRecordCellInstances: CompareFlatCTProc; <> CompareIRProc: TYPE = PROC [CD.Rect, CD.Rect] RETURNS [BOOL]; <> <> <<>> CompareInX: CompareIRProc; CompareInY: CompareIRProc; CompareReverseInX: CompareIRProc; CompareReverseInY: CompareIRProc; CompareOrigin: CompareIRProc; -- If y1=y2 THEN x1> EnumerateRoutedArea: PROC [obj: CD.Object, eachRoutingCell, eachPatchWorkCell: EachComponentProc _ NIL, trans: CoreGeometry.Transformation _ []] RETURNS [quit: BOOL]; DecorateRoutedArea: PROC [cellType: CellType, obj: CD.Object, wireToLabels: PROC [Wire] RETURNS [LIST OF Route.Label], compareIR: CompareIRProc _ CompareOrigin, compareCT: CompareFlatCTProc _ CompareRecordCellInstances]; <> <<>> MakeRoutingCell: PROC [cell: CD.Object, publicToLabel: PROC [Rope.ROPE] RETURNS [Route.Label]] RETURNS [routingCell: CD.Object]; <> <> <> <> <> <> <<>> Segments: TYPE = LIST OF Segment; Segment: TYPE = RECORD [label: Route.Label, min, max: INT, layer: CD.Layer]; <> ExtendSegmentProc: TYPE = PROC [label: Route.Label, size: INT, layer: CD.Layer, side: Side, extension: INT] RETURNS [CD.Object _ NIL]; <> <> <<>> ExtendSegment: ExtendSegmentProc; <> <> <<>> ExtendObject: PROC [enumerateSegments: PROC [PROC [Segment]], size: CD.Position, side: Side, extendProc: ExtendSegmentProc _ ExtendSegment] RETURNS [extension: CD.Object]; <> <> <> <<>> SetExtend: PROC [cellType: CellType, bottom, right, top, left: INT _ 0]; <> <> <<$RawChannelRoute, that just assumes a record of type ChannelInfo under the $ChannelInfo property on the cellType;>> <<$ChannelRoute, that calls an attribute proc that computes ChannelInfo from schematics decorations. Details of the parameter specification are in documentation.>> <> <<$Trunk: ATOM or ROPE denoting a layer. Defaults to Metal.>> <<$Branch: ATOM or ROPE denoting a layer. Defaults to Metal2.>> <<$Justify: ATOM specifies $TopRight, $BottomLeft.>> <<$DesignRules: ATOM specifies the design rules to use. Defaults to $cmosB.>> <<$TotalWidth: REF INT specifies the total width of the channel, in lambdas. Defaults means minimum size channel.>> <> <<$w: a REF INT, specifies a larger than default channel trunk wire width.>> <<>> ChannelInfo: TYPE = REF ChannelInfoRec; ChannelInfoRec: TYPE = RECORD [ direction: DABasics.Direction, -- Horizontal => that the channel will be abutted in Y. tech: REF, -- Technology for that channel. trunk: REF, -- From side to side, "poly", "metal" or "metal2". branch: REF, -- From cell to cell. "poly", "metal" or "metal2" justify: BOOL _ TRUE, -- Provokes automatic stretch justifyBottomOrLeft: BOOL _ TRUE, -- For extension, defines side opposite to the extension. bottomOrLeftWires: Core.Wires _ NIL, -- ** topOrRightWires: Core.Wires _ NIL, -- **. totalWidth: INT _ 0 -- lambda width of channel plus objects; 0 => min ]; <<** Indicates the order in which those wires appear at the bottom and top. Might be structured, but then only atomic wires are taken into account. All atomic wires must be part of the internal of the cell.>> <> <> <<$Stack derives layout information from schematic geometry with its attribute proc.>> <<$RawStack assumes a record of type StackForm under the cellType property $StackForm.>> <> <<$Trunk: ATOM OR ROPE denoting a layer. If ambiguous, defaults to Metal.>> <<$Branch: ATOM OR ROPE denoting a layer. If ambiguous, defaults to Metal2.>> <<$Justify: ATOM specifies $TopRight, $BottomLeft, $BestFit>> <<$HorizontalStack, REF specifies when non-NIL a horizontal stack. This is used only in the degenerate case of a stack containing just one subcell. It essentially determines which ends of the subcell can have channel routes.>> <> <<$w: a REF INT, specifies a larger than default channel trunk wire width.>> <<>> StackForm: TYPE = REF StackFormRec; StackFormRec: TYPE = RECORD[ inX: BOOL, justification: Justification _ bottomLeft, trunkLayer: CD.Layer _ CD.commentLayer, branchLayer: CD.Layer _ CD.commentLayer, min: INT _ LAST[INT], max: INT _ FIRST[INT], auxLabels: SymTab.Ref _ NIL, sec: LIST OF StackSection _ NIL ]; StackSection: TYPE = RECORD[ -- either chan=NIL OR abuts=NIL but not both chan: REF StackChanRec _ NIL, abuts: LIST OF StackAbutRec _ NIL, abutMin: INT _ LAST[INT], abutMax: INT _ FIRST[INT]]; StackAbutRec: TYPE = RECORD[ inst: INT _ -1, off: INT _ 0, laySize: LaySize _ [0,0], minPins: WirePins _ NIL, maxPins: WirePins _ NIL, firstPins: WirePins _ NIL, lastPins: WirePins _ NIL ]; StackChanRec: TYPE = RECORD[ minPins: WirePins _ NIL, maxPins: WirePins _ NIL, firstPins: WirePins _ NIL, lastPins: WirePins _ NIL ]; LaySize: TYPE = RECORD[width, height: INT]; -- width: across stack, height: along stack <> <> <<$ChangeLayers derives layout information from schematic geometry with its attribute proc.>> <<$RawChangeLayers assumes a record of type ChangeLayersForm under the cellType property $ChangeLayersForm. >> <> <<$w: a REF INT, specifies a larger than default bus width.>> <<>> ChangeLayersForm: TYPE = REF ChangeLayersFormAry; ChangeLayersFormAry: TYPE = RECORD[ vert: CD.Layer _ CD.commentLayer, ary: ARRAY Side OF ChangeLayersFormRec ]; ChangeLayersFormRec: TYPE = RECORD[ pins: WirePins _ NIL, min: INT _ LAST[INT], max: INT _ FIRST[INT], width: INT _ 0, busMin: INT _ LAST[INT], busMax: INT _ FIRST[INT], bus: Wire _ NIL, busSize: INT _ 0, busLo: BOOL _ FALSE, busHi: BOOL _ FALSE]; <> <> LayPins: PROC[cellType: CellType, side: Side] RETURNS[pins: WirePins]; SchPins: PROC[cellType: CellType, side: Side] RETURNS[pins: WirePins]; ReverseWirePins: PROC[pins: WirePins] RETURNS[rev: WirePins]; GlobalWires: PROC[cellType: CellType] RETURNS[wires: Core.Wires]; WirePinWires: PROC[pins: WirePins] RETURNS[wires: Core.Wires]; FilterPins: PROC[pins: WirePins, wires0, wires1: Core.Wires] RETURNS[sel: WirePins _ NIL]; <> FindBestOffset: PROC[pins1, pins2: WirePins] RETURNS[offSet: INT]; -- for min routing SchMappedIR: PROC[inst: CoreClasses.CellInstance] RETURNS[ir: CD.Rect]; GetCellTypePropLayer: PROC[cellType: CellType, key: ATOM, default: REF _ NIL] RETURNS[layer, other: CD.Layer_CD.commentLayer]; GetRoutingLayer: PROC[pins: WirePins] RETURNS[layer: CD.Layer]; GetJustification: PROC[cellType: CellType] RETURNS[justification: Justification]; Justification: TYPE = {bottomLeft, topRight, bestFit}; InstanceArray: TYPE = REF InstanceArraySeq; InstanceArraySeq: TYPE = RECORD[SEQUENCE size: CARDINAL OF InstanceRow]; InstanceRow: TYPE = REF InstanceRowSeq; InstanceRowSeq: TYPE = RECORD[SEQUENCE size: CARDINAL OF CoreClasses.CellInstance]; ShowInstanceArray: PROC[ia: InstanceArray]; SortedInstanceArray: PROC[cellType: CellType] RETURNS[ia: InstanceArray]; Sort2DInstances: PROC[cellType: CellType]; -- priority: overlapY then Left else Bot MakeChannel: PROC[ parent: CellType, chanIndex: INT, -- Insures unique names in auxLabelTab for multi chans. auxLabelTab: SymTab.Ref, -- LIST OF Route.Label for broken nets. trunkLength: INT, -- firstPins/lastPins min/max must be IN [0..trunkLength] branchLength: INT, -- minPins/maxPins min/max ignored (for now) trunkDirection: DABasics.Direction, horizLayer: CD.Layer, vertLayer: CD.Layer, minPins: WirePins _ NIL, -- IF trunkDirection=vertical THEN bottom maxPins: WirePins _ NIL, -- IF trunkDirection=vertical THEN top firstPins: WirePins _ NIL, -- IF trunkDirection=vertical THEN left lastPins: WirePins _ NIL ] -- IF trunkDirection=vertical THEN right RETURNS[channel: CD.Object]; END.