The cell has 12846 placable elements
Size is 50913408 sq microns = 50.9134 sq mm.
2304 dLatch =>  33.9% of total area.
2997 tstDriver =>  19.6% of total area.
895 ff =>  14.6% of total area.
4170 inv =>  13.6% of total area.
454 xor2 =>   4.5% of total area.
636 invBuffer =>   3.1% of total area.
81 ffEn =>   2.0% of total area.
301 nor2 =>   1.5% of total area.
177 nor4 =>   1.4% of total area.
210 nor3 =>   1.4% of total area.
150 a22o2i =>   1.2% of total area.
187 nand2 =>   0.9% of total area.
73 xnor2 =>   0.7% of total area.
61 nand3 =>   0.4% of total area.
44 nand4 =>   0.4% of total area.
26 or3 =>   0.2% of total area.
32 or2 =>   0.2% of total area.
22 and2 =>   0.1% of total area.
12 or4 =>   0.1% of total area.
8 and3 =>   0.1% of total area.
5 and4 =>   0.0% of total area.
1 a21o2i =>   0.0% of total area.

Statistics on MemoryController:
2304 DLatch =>  33.9% of total area.
2912 TstDriver =>  19.0% of total area.
805 FlipFlop =>  13.2% of total area.
3805 Inv =>  12.4% of total area.
454 Xor2 =>   4.5% of total area.
8 CounterUp b=4 =>   1.8% of total area.
161 Nor n=3 =>   1.1% of total area.
119 Nor n=4 =>   1.0% of total area.
2 RegisterR b=15 =>   1.0% of total area.
172 Nor n=2 =>   0.8% of total area.
2 Register b=16 =>   0.8% of total area.
32 FlipFlopEnable =>   0.8% of total area.
2 MuxN1 n=16 =>   0.7% of total area.
83 Driver d=8 =>   0.7% of total area.
131 Nand n=2 =>   0.6% of total area.
32 InvDriver d=16 =>   0.6% of total area.
1 CounterUp b=9 =>   0.5% of total area.
1 Decoder a=4 s=16 =>   0.4% of total area.
57 Nand n=3 =>   0.4% of total area.
43 Nand n=4 =>   0.4% of total area.
2 InvMux b=16 =>   0.3% of total area.
4 Buffer d=32 =>   0.3% of total area.
1 MuxD n=5 b=5 =>   0.3% of total area.
1 CounterUp b=5 =>   0.3% of total area.
1 Register b=10 =>   0.3% of total area.
3 DecoderS a=3 s=8 =>   0.2% of total area.
15 Driver d=10 =>   0.2% of total area.
1 Mux n=2 b=16 =>   0.2% of total area.
2 Decoder a=3 s=8 =>   0.2% of total area.
4 Comparator b=4 =>   0.2% of total area.
1 RegisterR b=5 =>   0.2% of total area.
1 MuxN1 n=8 =>   0.2% of total area.
1 DecoderS a=4 s=10 =>   0.2% of total area.
30 InvDriver d=8 =>   0.1% of total area.
3 FlipFlopMR =>   0.1% of total area.
3 Decoder a=2 s=4 =>   0.1% of total area.
1 CKBuffer d=48 numRows=40  =>   0.1% of total area.
1 RegisterSimple b=7 =>   0.1% of total area.
11 Xnor2 =>   0.1% of total area.
16 Or n=2 =>   0.1% of total area.
5 Buffer d=8 =>   0.1% of total area.
3 DecoderS a=2 s=4 =>   0.1% of total area.
12 A22o2i =>   0.1% of total area.
9 Or n=4 =>   0.1% of total area.
13 And n=2 =>   0.1% of total area.
2 RegisterR b=1 =>   0.1% of total area.
1 MuxDN1 n=8 =>   0.1% of total area.
1 Register b=3 =>   0.1% of total area.
1 CKBuffer d=28 numRows=7  =>   0.1% of total area.
3 Nor n=7 =>   0.1% of total area.
1 Mux n=2 b=5 =>   0.1% of total area.
1 DecoderS a=3 s=5 =>   0.1% of total area.
2 Register b=1 =>   0.1% of total area.
7 Or n=3 =>   0.1% of total area.
7 And n=3 =>   0.1% of total area.
1 Register b=2 =>   0.1% of total area.
9 Buffer d=2 =>   0.0% of total area.
1 MuxN1 n=4 =>   0.0% of total area.
1 Buffer d=15 =>   0.0% of total area.
2 Driver d=24 =>   0.0% of total area.
2 Driver d=13 =>   0.0% of total area.
2 MuxN1 n=2 =>   0.0% of total area.
1 CKBuffer d=12 numRows=40  =>   0.0% of total area.
1 Driver d=26 =>   0.0% of total area.
1 InvDriver d=24 =>   0.0% of total area.
1 InvDriver d=20 =>   0.0% of total area.
1 CKBuffer d=7 numRows=7  =>   0.0% of total area.
1 Driver d=20 =>   0.0% of total area.
1 And n=4 =>   0.0% of total area.
1 A21o2i =>   0.0% of total area.
1 InvDriver d=4 =>   0.0% of total area.