DIRECTORY Core, RefTab; CoreClasses: CEDAR DEFINITIONS = BEGIN OPEN Core; recordCellClass: CellClass; RecordCellType: TYPE = REF RecordCellTypeRec; RecordCellTypeRec: TYPE = RECORD [ internal: WireSeq, instances: SEQUENCE size: NAT OF CellInstance]; CellInstance: TYPE = REF CellInstanceRec; CellInstanceRec: TYPE = RECORD [ actual: WireSeq, type: CellType, properties: Properties _ NIL]; CellInstances: TYPE = LIST OF CellInstance; CreateRecordCell: PROC [public: WireSeq, internal: WireSeq, instances: LIST OF CellInstance, name: ROPE _ NIL, props: Properties _ NIL, giveNames: BOOL _ FALSE] RETURNS [recordCell: CellType]; CreateInstance: PROC [actual: WireSeq, type: CellType, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [instance: CellInstance]; SetCellInstanceName: PROC [instance: CellInstance, name: ROPE] RETURNS [sameInstance: CellInstance]; GetCellInstanceName: PROC [instance: CellInstance] RETURNS [name: ROPE]; CorrespondingActual: PROC [instance: CellInstance, public: Wire] RETURNS [actual: Wire _ NIL]; CreatePermutedRecordCell: PROC [iconPublic: WireSeq, schCell: CellType, table: RefTab.Ref, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [recordCell: CellType]; ReverseCellInstances: PROC [instances: CellInstances] RETURNS [rev: CellInstances _ NIL]; InstanceIndex: PROC [recordCell: CellType, instance: CellInstance] RETURNS [index: INT _ -1]; transistorCellClass: CellClass; Transistor: TYPE = REF TransistorRec; TransistorRec: TYPE = RECORD [ type: TransistorType _ nE]; TransistorType: TYPE = {nE, pE, nD}; TransistorPort: TYPE = MACHINE DEPENDENT {gate(0), ch1(1), ch2(2), Vdd(3)}; transistorTypeNames: ARRAY TransistorType OF ROPE; transistorPortNames: ARRAY TransistorPort OF ROPE; lengthProp: ATOM; -- REF INT widthProp: ATOM; -- REF INT CreateTransistor: PROC [type: TransistorType, length: INT _ -1, width: INT _ -1, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [transistor: CellType]; unspecifiedCellClass: CellClass; CreateUnspecified: PROC [public: WireSeq, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [cellType: CellType]; sequenceCellClass: CellClass; SequenceCellType: TYPE = REF SequenceCellTypeRec; SequenceCellTypeRec: TYPE = RECORD [ base: CellType, count: NAT, sequence: SequenceSet _ NIL, flatSequence: SequenceSet _ NIL, stitch: StitchSet _ NIL]; SequenceSet: TYPE = REF SequenceSetRec; SequenceSetRec: TYPE = RECORD [set: SEQUENCE length: NAT OF NAT]; StitchSet: TYPE = REF StitchSetRec; StitchSetRec: TYPE = RECORD [set: SEQUENCE length: NAT OF Stitch]; Stitch: TYPE = RECORD [this, that: NAT]; CreateSequence: PROC [args: SequenceCellType, name: ROPE _ NIL, props: Properties _ NIL] RETURNS [cellType: CellType]; END. (CoreClasses.mesa Copyright س 1985, 1987 by Xerox Corporation. All rights reserved. Bertrand Serlet, April 6, 1987 3:08:58 pm PDT Pradeep Sindhu December 2, 1985 3:36:33 pm PST Barth, March 31, 1987 4:43:20 pm PST Spreitzer, January 10, 1986 4:03:48 pm PST Mike Spreitzer February 27, 1987 2:33:21 pm PST Theory This interface defines a set of Classes of general interest. Record The record class describes the structuring mechanism which takes a collection of cell types of various classes and binds them together. Some invariants must be established by programs which create this data structure: 1) The actual wire sequence of an instance must conform to the public wire sequence of the cell type which is being instantiated. An actual wire may converge more than a public wire and still be considered to conform. This allows more than one wire of a public to be attached to the same actual. 2) The actual wire sequence record may not be shared with anything else. Every actual wire must reachable from the containing cell type's internal wire sequence. 3) The public wire sequence record may not be shared with anything else. Every public wire must be reachable from the cell type's internal wire sequence. 4) The internal wire sequence record may not be shared with anything else. An internal wire must be treated as immutable once it is part of a record cell because of the CoreOps naming strategy. So must the internal wire sequence. 5) Cell types may not share any part of any internal wire. internal.size=0 => empty internal instances.size may be 0 actual.size=0 => empty actual Checks that actuals conform to the sub publics and that actuals and public are part of the internals. name, if non NIL, has precedence over props. The giveNames option (when TRUE) will set short names for actual which are unnamed (and which have unnamed ancestors), when the corresponding sub publics all have the same name (if any), and when this name is not contradictory with any other name. name, if non NIL, has precedence over props. Returns the actual bound to the public in the instance, NIL if not found Creates a recordCell with only one instance of schCell and which public conform to iconPublic. Table is a table from publics of schCell to publics of iconPublic. Two different publics of schCell may map the same public of iconPublic. name, if non NIL, has precedence over props. Reverses a list of CellInstances Searches among all instances of recordCell for instance. -1 is returned if no such instance is found. Transistor Public wires: gate, ch1, ch2, IF type=pE THEN Vdd name, if non NIL, has precedence over props. length or width -1 => no corresponding property Please note that for pE transistors the name "Vdd" is misleading and that "well" might be more appropriate. Vdd was chosen to help schematics for which this port is usually connected to "Vdd". Unspecified Unspecified is the cell class that means to not specify structure. Cell types in this class are not necessarily leaves, nor composites --- their internal structure is unspecified. name, if non NIL, has precedence over props. Sequence Sequences describes the class of cellTypes made from a collection of cell instances of identical type bound together. Cell zero contributes its "this" to the public, the last cell contributes its "that" to the public, all intermediate cells have "this" bound to "that". Note that if count is one or stitch is NIL then there will not be any internal nodes. Never put a wire into more than one set. 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