CreateRamArray:
PUBLIC
PROC [cx: Sisyph.Context]
RETURNS [cellType: CellType] = {
insts: CellInstances ← NIL;
ramRow: CellType ← Sisyph.ES["RamRow.sch", cx];
flipRomRow: CellType ← PWCore.RotateCellType[CreateRomRow[cx], $FlipY];
flipRamRow: CellType ← PWCore.RotateCellType[ramRow, $FlipY];
IF constAdr MOD 2=0 THEN ERROR; -- else change the orientation of the rom row!
FOR i:
NAT
IN [0..nRows)
DO
insts ←
CONS[
Instance[
SELECT
TRUE
FROM
i=constAdr => flipRomRow,
i MOD 2 = 0 => ramRow,
ENDCASE => flipRamRow,
["selA", Index["selA", i]], ["selB", Index["selB", i]], ["selC", Index["selC", i]]
],
insts];
ENDLOOP;
cellType ← Cell[name: "RamArray",
public: Wires["Vdd", "Gnd", Seq["selA", nRows], Seq["selB", nRows], Seq["selC", nRows],
Seq["naBit", nbits, Seq[size: 4]], Seq["bBit", nbits, Seq[size: 4]], Seq["cBit", nbits, Seq[size: 4]], Seq["ncBit", nbits, Seq[size: 4]] ],
instances: insts];
PWCore.SetAbutY[cellType];
};
CreateRomRow:
PROC [cx: Sisyph.Context]
RETURNS [cellType: CellType] = {
rom0: CellType ← Sisyph.ES["Rom0Cell.sch", cx];
rom1: CellType ← Sisyph.ES["Rom1Cell.sch", cx];
stitch: CellType ← Sisyph.ES["RamStitch.sch", cx];
rom0000: CellType ← CreateRomQuad[rom0, rom0, rom0, rom0, stitch]; -- msb
rom0011: CellType ← CreateRomQuad[rom0, rom0, rom1, rom1, stitch];
rom0101: CellType ← CreateRomQuad[rom0, rom1, rom0, rom1, stitch]; -- lsb
-- 0 is msb, on the left, and must be at the beginning of the list
insts: CellInstances ← NIL;
insts ←
CONS[Instance[rom0101,
["naBit", Index["naBit", nbits-1]], ["bBit", Index["bBit", nbits-1]],
["cBit", Index["cBit", nbits-1]], ["ncBit", Index["ncBit", nbits-1]]], insts];
insts ←
CONS[Instance[rom0011,
["naBit", Index["naBit", nbits-2]], ["bBit", Index["bBit", nbits-2]],
["cBit", Index["cBit", nbits-2]], ["ncBit", Index["ncBit", nbits-2]]], insts];
FOR i:
NAT
DECREASING
IN [0..nbits-2)
DO
insts ←
CONS[Instance[rom0000,
["naBit", Index["naBit", i]], ["bBit", Index["bBit", i]],
["cBit", Index["cBit", i]], ["ncBit", Index["ncBit", i]]], insts];
ENDLOOP;
cellType ← Cell[name: "RomRow",
public: Wires[Seq["naBit", nbits, Seq[size: 4]], Seq["bBit", nbits, Seq[size: 4]], Seq["cBit", nbits, Seq[size: 4]], Seq["ncBit", nbits, Seq[size: 4]], "selA", "selB", "selC", "Vdd", "Gnd"],
instances: insts];
PWCore.SetAbutX[cellType];
};
CreateRomQuad:
PROC [b0, b1, b2, b3, stitch: CellType]
RETURNS [cellType: CellType] = {
rom0: CellInstance ← Instance[b0,
["naBit", "naBit[0]"], ["bBit", "bBit[0]"], ["cBit", "cBit[0]"], ["ncBit", "ncBit[0]"]];
ram1: CellInstance ← Instance[b1,
["naBit", "naBit[1]"], ["bBit", "bBit[1]"], ["cBit", "cBit[1]"], ["ncBit", "ncBit[1]"]];
ram2: CellInstance ← Instance[b2,
["naBit", "naBit[2]"], ["bBit", "bBit[2]"], ["cBit", "cBit[2]"], ["ncBit", "ncBit[2]"]];
ram3: CellInstance ← Instance[b3,
["naBit", "naBit[3]"], ["bBit", "bBit[3]"], ["cBit", "cBit[3]"], ["ncBit", "ncBit[3]"]];
s: CellInstance ← Instance[stitch];
cellType ← Cell[name: "RomQuadSt",
public: Wires["Vdd", "Gnd", "selA", "selB", "selC",
Seq["naBit", 4], Seq["bBit", 4], Seq["cBit", 4], Seq["ncBit", 4]],
instances: LIST [rom0, ram1, ram2, ram3, s]];
PWCore.SetAbutX[cellType];
};