CheckConnectivityCommand: Commander.CommandProc = {
argv: CommandTool.ArgumentVector ← CommandTool.Parse[cmd: cmd, starExpand:
FALSE
! CommandTool.Failed => {msg ← errorMsg; GO TO failed}];
instances: CD.InstanceList;
design: CD.Design;
file, shortName: ROPE;
out: IO.STREAM;
mode: Sinix.Mode;
cell: CellType;
nodeness: Wires;
IF argv.argc#2 THEN {msg ← Rope.Cat["Incorrect syntax.\n", commandProcDoc]; GO TO failed};
file ← CDEnvironment.FindFile[argv[1], ".dale"];
shortName ← FileNames.GetShortName[file];
design ← PW.OpenDesign[file];
RoutingCheck.Check[design]; -- check all routing cells
out ← ViewerIO.CreateViewerStreams[
name: IO.PutFR["Connectivity check of %g.", IO.rope[shortName]],
backingFile: Rope.Cat[Rope.Substr[shortName, 0, Rope.Length[shortName]-5], ".cclog"]
].out;
instances ← CDOps.InstList[design];
IF instances=NIL OR instances.rest#NIL THEN ERROR;
mode ← SinixOps.GetExtractMode[tech: design.technology];
cell ← NARROW [Sinix.Extract[instances.first.ob, mode].result];
IO.PutF[out, "Checking connectivity of %g.\n", IO.rope[CoreOps.GetCellTypeName[cellType: cell]]];
nodeness ← GetNodeness[decoration: mode.decoration, touch: mode.touchProc, cell: cell !
InternalDisconnection => {
name: ROPE ← NIL;
name ← CoreOps.GetFullWireName[root:
NARROW [cell.data, CoreClasses.RecordCellType].internal, wire: wire !
ANY => {
IO.Put[out, IO.rope["<ERROR in CoreOps.GetFullWireName>"]]; CONTINUE
}
];
IO.PutF[out, "SIGNAL: Wire %g in cell %g is disconnected internally.\n", IO.rope[name], IO.rope[CoreOps.GetCellTypeName[cellType: cell]]];
RESUME
}
];
IF nodeness =
NIL
THEN
IO.PutF[out, "Cell %g contains no disconnected public wires.\n", IO.rope[CoreOps.GetCellTypeName[cellType: cell]]]
ELSE {
IO.PutF[out, "Cell %g contains the following disconnected public wires:\n", IO.rope[CoreOps.GetCellTypeName[cellType: cell]]];
FOR wires: Wires ← nodeness, wires.rest
UNTIL wires =
NIL
DO
IO.PutF[out, " %g's pins are in %g bags.\n", IO.rope[CoreOps.GetFullWireName[root: cell.public, wire: wires.first]], IO.int[Bagness.BagCount[bagList: GetBagnessProp[decoration: mode.decoration, touch: mode.touchProc, wire: wires.first]]]];
ENDLOOP;
};
IO.Close[out];
EXITS
failed => {result ← $Failure};
};
CheckConnectivity:
PROC [command: CDSequencer.Command] = {
Extracts selected layout, checks connectivity of public wires, and highlights any disconnected ones.
design: CD.Design = command.design;
mode: Sinix.Mode = SinixOps.GetExtractMode[tech: design.technology];
decoration: Decoration = mode.decoration;
touch: TouchProc = mode.touchProc;
disconnectedInternals: LIST OF RECORD[cell: CellType, wire: Wire] ← NIL;
root, cell: CellType;
trans: Transformation;
[root: root, cell: cell, trans: trans] ← SinixOps.SelectedCellType[design: design, mode: mode];
IF root #
NIL
THEN {
nodeness: Wires ← GetNodeness[decoration: decoration, touch: touch, cell: cell !
InternalDisconnection => {
TerminalIO.PutRopes[t1: "SIGNAL: Wire ", t2: CoreOps.GetFullWireName[root:
NARROW[cell.data, CoreClasses.RecordCellType].internal, wire: wire !
ANY => {
TerminalIO.PutRope[text: "<ERROR in CoreOps.GetFullWireName>"];
CONTINUE
}
]];
TerminalIO.PutRopes[t1: " in cell ", t2: CoreOps.GetCellTypeName[cellType: cell], t3: " is disconnected internally.\n"];
disconnectedInternals ← CONS[[cell: cell, wire: wire], disconnectedInternals];
RESUME
}
];
TerminalIO.PutRope[text: CoreOps.GetCellTypeName[cellType: cell]];
IF nodeness =
NIL
THEN
TerminalIO.PutRope[text: " contains no disconnected public wires.\n"]
ELSE {
AddInstance: CoreGeometry.EachInstanceProc = {
Transforms instance and tacks it onto instances.
instances ← CONS[CoreGeometry.Transform[trans: trans, instance: instance], instances]
};
instances: CoreGeometry.Instances ← NIL;
TerminalIO.PutRope[text: " contains the following disconnected public wires:\n"];
FOR wires: Wires ← nodeness, wires.rest
UNTIL wires =
NIL
DO
TerminalIO.PutRopes[t1: " ", t2: CoreOps.GetFullWireName[root: cell.public, wire: wires.first]];
TerminalIO.PutF1[format: "'s pins are in %g bags.\n", value: IO.int[Bagness.BagCount[bagList: GetBagnessProp[decoration: decoration, touch: touch, wire: wires.first]]]];
[] ← CoreGeometry.EnumerateAllGeometry[decoration: decoration, cell: cell, wire: wires.first, eachInstance: AddInstance]
ENDLOOP;
TerminalIO.PutRope[text: " ** End List **\n"];
SinixOps.HighlightDesign[design: design, highlight: SinixOps.HighLightListInst[instances: instances]]
}
}
};