[_CD4_]<datools7.0>CongSC25>SCImpl.mesa!3

SCImpl.mesa

Bryan Preas, August 14, 1986 5:07:05 pm PDT

Last Edited by: Bryan Preas June 15, 1987 6:21:04 pm PDT

Christian Le Cocq June 24, 1987 10:46:09 am PDT

DIRECTORY

CD, CDSimpleRules, Core, CoreFlat, CoreGeometry, CoreOps, CoreProperties, CoreRoute, Process, PWCore, Rope, Route, RTCoreUtil, SC, SCChanUtil, SCInitialPlace, SCInstUtil, SCPlaceUtil, SCPrivate, SCRowUtil, SCSmash, SCUtil, Sinix, Sisyph, TWOps;

SCImpl: CEDAR PROGRAM

IMPORTS CD, CDSimpleRules, CoreFlat, CoreGeometry, CoreOps, CoreProperties, CoreRoute, Process, PWCore, Rope, Route, RTCoreUtil, SC, SCChanUtil, SCInitialPlace, SCInstUtil, SCPlaceUtil, SCPrivate, SCRowUtil, SCSmash, SCUtil, Sisyph, TWOps

EXPORTS SC

SHARES SC = {

debug: BOOLEAN ← FALSE;

Errors

Error: PUBLIC ERROR[errorType: SC.ErrorType ← callingError, explanation: Rope.ROPE ← NIL] = CODE;

Signal: PUBLIC SIGNAL[signalType: SC.ErrorType ← callingError, explanation: Rope.ROPE ← NIL] = CODE;

Design Rules

CreateDesignRules: PUBLIC PROC [technologyKey: ATOM, horizLayer, vertLayer: Rope.ROPE, rowDirection: SC.Direction] RETURNS [designRules: SC.DesignRules] =

Define the standard cell design rules. technologyKey values are predefinded for now. horizLayer, vertLayer should be "poly", "metal" or "metal2".

BEGIN

hLayer: CD.Layer ← CDSimpleRules.GetLayer[technologyKey, horizLayer];

vLayer: CD.Layer ← CDSimpleRules.GetLayer[technologyKey, vertLayer];

technology: CD.Technology ← CD.FetchTechnology[technologyKey];

designRules ← NEW[SC.DesignRulesRec ← [horizLayer: horizLayer, vertLayer: vertLayer, rowParms: Route.DefaultDesignRulesParameters[technology, hLayer, vLayer, rowDirection], sideParms: Route.DefaultDesignRulesParameters[technology, hLayer, vLayer, rowDirection]]];

designRules.rowRules ← Route.DefaultDesignRules[designRules.rowParms];

designRules.sideRules ← Route.DefaultDesignRules[designRules.sideParms];

END;

Standard Cell Handles and Results

CreateHandle: PUBLIC PROC [cellType: Core.CellType, flattenCellType: RTCoreUtil.FlattenCellTypeProc, libName: Rope.ROPE, designRules: SC.DesignRules, name: Rope.ROPE, decoration: CoreGeometry.Decoration] RETURNS [handle: SC.Handle] =

Create a standard cell design. The standard cell design definition includes the design rules (conductor and via widths and spacings) and the circuit definition.

BEGIN

parms: SCPrivate.Parms ← NARROW[NEW[SCPrivate.ParmsRec], SCPrivate.Parms];

IF designRules = NIL THEN SC.Signal[callingError, "No design rules."];

IF cellType = NIL THEN SC.Signal[callingError, "No Core cell type."];

handle ← NEW[SC.HandleRec];

handle.name ← IF name # NIL THEN name ELSE CoreOps.GetCellTypeName[cellType];

handle.rules ← designRules;

handle.coreCellType ← cellType;

parms.libName ← libName;

handle.parms ← parms;

set up the layout data

IF ~SCPrivate.SetUpLayout[handle, cellType] THEN

SC.Signal[callingError, "Unable to construct layout data"];

set up the structure data

IF ~SCPrivate.GetStructure[handle, cellType, flattenCellType, decoration] THEN

SC.Signal[callingError, "Unable to construct structure data"];

END;

Standard Cell Optimization and Construction

InitialPlace: PUBLIC PROC [handle: SC.Handle, numRows: NAT ← 0] = {

Determine an initial placement for the instances.

layoutData: SCPrivate.LayoutData ← NARROW[handle.layoutData];

p: Process.Priority ← Process.GetPriority[];

Process.SetPriority[Process.priorityBackground];

SCSmash.RemoveSmash[handle];

SCPlaceUtil.ClrCurPlac[handle, TRUE];

SCInitialPlace.PrePlace[handle: handle, numRows: numRows, routingFactor: 2.5, initialized: TRUE];

SCInitialPlace.RowInit[handle];

SCInitialPlace.PosInit[handle];

[layoutData.lgRows.maxRowWidth, layoutData.lgRows.numMaxRows] ← SCRowUtil.FindMaxRow[handle];

SCChanUtil.InitChanWidths[handle];

SCInstUtil.AsgnChanPos[handle];

layoutData.initTotWidth ← layoutData.totWidth;

layoutData.initTotHeight ← layoutData.totHeight;

IF debug THEN SCPlaceUtil.WriteCurPlace[handle];

[] ← SCUtil.WriteResults["End initial placement\n initial size: ", handle, 0];

Process.SetPriority[p]};

PosImprove: PUBLIC PROC [handle: SC.Handle, maxCycles: INT] = {

Improve the positions of instances whithin rows.

p: Process.Priority ← Process.GetPriority[];

Process.SetPriority[Process.priorityBackground];

SCPrivate.PosImprove[handle, areaFom, maxCycles];

Process.SetPriority[p]};

PosImproveWL: PUBLIC PROC [handle: SC.Handle, maxCycles: INT] = {

Improve the positions of instances whithin rows using wire lenght as figure of merit.

p: Process.Priority ← Process.GetPriority[];

Process.SetPriority[Process.priorityBackground];

SCPrivate.PosImprove[handle, wlFom, maxCycles];

Process.SetPriority[p]};

OrientImprove: PUBLIC PROC [handle: SC.Handle, maxCycles: INT] = {

Improve the orientation of instances.

p: Process.Priority ← Process.GetPriority[];

Process.SetPriority[Process.priorityBackground];

SCPrivate.OrientImprove[handle, areaFom, maxCycles];

Process.SetPriority[p]};

OrientImproveWL: PUBLIC PROC [handle: SC.Handle, maxCycles: INT] = {

Improve the orientation of instances using wire lenght as figure of merit.

p: Process.Priority ← Process.GetPriority[];

Process.SetPriority[Process.priorityBackground];

SCPrivate.OrientImprove[handle, wlFom, maxCycles];

Process.SetPriority[p]};

FTImprove: PUBLIC PROC [handle: SC.Handle, maxCycles: INT] = {

Improve the positions of instances whithin rows.

p: Process.Priority ← Process.GetPriority[];

Process.SetPriority[Process.priorityBackground];

SCPrivate.FTImprove[handle, wlFom, maxCycles];

Process.SetPriority[p]};

SAInitialPlace: PUBLIC PROC [handle: SC.Handle, widthFactor: REAL, seed: INT] RETURNS [initialResult: SC.SAInitialResult] = {

Initialize for simulated annealing improvement.

p: Process.Priority ← Process.GetPriority[];

Process.SetPriority[Process.priorityBackground];

initialResult ← SCPrivate.SAInitialPlace[handle, widthFactor, seed];

Process.SetPriority[p]};

SAGetParms: PUBLIC PROC [handle: SC.Handle, initialResult: SC.SAInitialResult, cellType: Core.CellType] RETURNS [saParms: SC.SAParms] = {

determine parameters for simulated placement.

p: Process.Priority ← Process.GetPriority[];

Process.SetPriority[Process.priorityBackground];

saParms ← SCPrivate.SAGetParms[handle, initialResult, cellType];

Process.SetPriority[p]};

SAPlaceImprove: PUBLIC PROC [handle: SC.Handle, saParms: SC.SAParms, widthFactor: REAL, seed: INT] = {

Improve the placement for the instances (one at a time) by simulated annealing.

p: Process.Priority ← Process.GetPriority[];

Process.SetPriority[Process.priorityBackground];

SCPrivate.SAPlaceImprove[handle, saParms, widthFactor, seed];

Process.SetPriority[p]};

SAPlaceImproveM: PUBLIC PROC [handle: SC.Handle, saParms: SC.SAParms, widthFactor: REAL, seed: INT] = {

Improve the placement for the instances (one at a time) by simulated annealing.

p: Process.Priority ← Process.GetPriority[];

Process.SetPriority[Process.priorityBackground];

SCPrivate.SAPlaceImproveM[handle, saParms, widthFactor, seed];

Process.SetPriority[p]};

PlaceImprove: PUBLIC PROC [handle: SC.Handle, maxCycles: INT] = {

Improve the placement for the instances by exhaustive search.

p: Process.Priority ← Process.GetPriority[];

Process.SetPriority[Process.priorityBackground];

SCPrivate.PlaceImprove[handle, maxCycles];

Process.SetPriority[p]};

GlobalRoute: PUBLIC PROC [handle: SC.Handle] = {

Determine strategic paths for the wiring that must cross cell rows.

p: Process.Priority ← Process.GetPriority[];

Process.SetPriority[Process.priorityBackground];

SCSmash.RemoveSmash[handle];

SCSmash.SmashAllNets[handle, FALSE];

Process.SetPriority[p]};

DetailRoute: PUBLIC PROC [handle: SC.Handle] RETURNS [result: SC.Result] = {

Determine actual wiring paths.

p: Process.Priority ← Process.GetPriority[];

Process.SetPriority[Process.priorityBackground];

result ← SCPrivate.DetailRoute[handle];

Process.SetPriority[p]};

CreateLayout: PUBLIC PROC [technologyKey: ATOM, horizLayer, vertLayer: Rope.ROPE, rowDirection: SC.Direction, numRows: NAT, cellType: Core.CellType, flattenCellType: RTCoreUtil.FlattenCellTypeProc, libName: Rope.ROPE ← NIL, name: Rope.ROPE ← NIL] RETURNS [object: CD.Object] = {

Create a standard cell object by performing the above operations

result: SC.Result;

widthFactor: REAL ← MAX[1.0, MIN[2.0, RTCoreUtil.GetCoreRealProp[cellType, SC.widthFactorProp, 1.1]]];

designRules: SC.DesignRules ← SC.CreateDesignRules[technologyKey, horizLayer, vertLayer, rowDirection];

handle: SC.Handle ← SC.CreateHandle[cellType, flattenCellType, libName, designRules, name, extractMode.decoration];

SC.InitialPlace[handle, RTCoreUtil.GetCoreIntProp[cellType, SC.numRows, 0]];

SC.SAPlaceImprove[handle, SC.SAGetParms[handle, SC.SAInitialPlace[handle, widthFactor], cellType], widthFactor];

SC.GlobalRoute[handle];

result ← SC.DetailRoute[handle];

RETURN [result.object]};

Destroy: PUBLIC PROC [handle: SC.Handle] ~ {

Remove circular references so garbage collection can work

SCPrivate.DestroyLayout[handle];

SCPrivate.DestroyStructure[handle];

SCUtil.DestroyRules[handle];

SCUtil.DestroyParms[handle];

handle.name ← NIL;

handle.coreCellType ← NIL};

PWCore Interface

-- The cellType to layout is a record cellType containing elements from MSI; the layout proc flattens the Core description and calls the standard cell router. Placement is obtained from timberwolf.

StandardCellRoute: PUBLIC PWCore.LayoutProc = {

result: SC.Result;

hMaterial: Rope.ROPE ← "metal";

vMaterial: Rope.ROPE ← "metal2";

widthFactor: REAL ← MAX[1.0, MIN[2.0, RTCoreUtil.GetCoreRealProp[cellType, SC.widthFactorProp, 1.1]]];

rules: SC.DesignRules ← SC.CreateDesignRules[technologyKey, hMaterial, vMaterial, horizontal];

handle: SC.Handle ← SC.CreateHandle[cellType: cellType, flattenCellType: RTCoreUtil.defaultFlatten, libName: libName, designRules: rules, decoration: extractMode.decoration];

CoreProperties.PutCellTypeProp[cellType, SC.handleAtom, handle];

SCUtil.ReadTWPlace[handle: handle];

SC.InitialPlace[handle, RTCoreUtil.GetCoreIntProp[cellType, SC.numRows, 0]];

initialResult ← SC.SAInitialPlace[handle, widthFactor];

saParms ← SC.SAGetParms[handle, initialResult, cellType];

SC.SAPlaceImprove[handle: handle, saParms: saParms, widthFactor: widthFactor];

SC.PlaceImprove[handle: handle, maxCycles: 1];

SC.GlobalRoute[handle];

SC.PlaceImprove[handle: handle, maxCycles: 1];

SC.PosImproveWL[handle, 1];

SC.OrientImproveWL[handle, 1];

SC.PosImprove[handle, 1];

SC.OrientImprove[handle, 1];

SCSmash.CheckFts[handle];

SCSmash.CheckExits[handle];

-- SC.FTImprove[handle, 10];

result ← SC.DetailRoute[handle];

RETURN[result.object]};

-- The cellType to layout is a record cellType containing elements from MSI; the layout proc flattens the Core description and calls the standard cell placer.

StandardCellPlace: PUBLIC PWCore.LayoutProc = {

hMaterial: Rope.ROPE ← "metal";

vMaterial: Rope.ROPE ← "metal2";

rules: SC.DesignRules ← SC.CreateDesignRules[technologyKey, hMaterial, vMaterial, horizontal];

handle: SC.Handle ← SC.CreateHandle[cellType: cellType, flattenCellType: RTCoreUtil.defaultFlatten, libName: libName, designRules: rules, decoration: extractMode.decoration];

CoreProperties.PutCellTypeProp[cellType, SC.handleAtom, handle];

SC.InitialPlace[handle, RTCoreUtil.GetCoreIntProp[cellType, SC.numRows, 0]];

SCUtil.WriteTWFiles[handle: handle];

RETURN[NIL]};

-- The cellType to layout is a record cellType containing elements from MSI; the layout proc flattens the Core description and calls the standard cell placer and router.

StandardCellLayout: PUBLIC PWCore.LayoutProc = {

result: SC.Result;

saParms: SC.SAParms;

initialResult: SC.SAInitialResult;

hMaterial: Rope.ROPE ← "metal";

vMaterial: Rope.ROPE ← "metal2";

widthFactor: REAL ← MAX[1.0, MIN[2.0, RTCoreUtil.GetCoreRealProp[cellType, SC.widthFactorProp, 1.1]]];

rules: SC.DesignRules ← SC.CreateDesignRules[technologyKey, hMaterial, vMaterial, horizontal];

handle: SC.Handle ← SC.CreateHandle[cellType: cellType, flattenCellType: RTCoreUtil.defaultFlatten, libName: libName, designRules: rules, decoration: extractMode.decoration];

CoreProperties.PutCellTypeProp[cellType, SC.handleAtom, handle];

SC.InitialPlace[handle, RTCoreUtil.GetCoreIntProp[cellType, SC.numRows, 0]];

initialResult ← SC.SAInitialPlace[handle, widthFactor];

saParms ← SC.SAGetParms[handle, initialResult, cellType];

SC.SAPlaceImprove[handle: handle, saParms: saParms, widthFactor: widthFactor];

SC.PlaceImprove[handle: handle, maxCycles: 1];

SC.GlobalRoute[handle];

SC.PlaceImprove[handle: handle, maxCycles: 1];

SC.PosImproveWL[handle, 1];

SC.OrientImproveWL[handle, 1];

SC.PosImprove[handle, 1];

SC.OrientImprove[handle, 1];

-- SCSmash.CheckFts[handle];

-- SCSmash.CheckExits[handle];

result ← SC.DetailRoute[handle];

RETURN[result.object]};

-- The cellType to layout is a record cellType containing elements from MSI; the layout proc flattens the Core description and calls the standard cell placer and router.

StandardCellLayoutTW: PUBLIC PWCore.LayoutProc = {

result: SC.Result;

hMaterial: Rope.ROPE ← "metal";

vMaterial: Rope.ROPE ← "metal2";

widthFactor: REAL ← MAX[1.0, MIN[2.0, RTCoreUtil.GetCoreRealProp[cellType, SC.widthFactorProp, 1.1]]];

rules: SC.DesignRules ← SC.CreateDesignRules[technologyKey, hMaterial, vMaterial, horizontal];

handle: SC.Handle ← SC.CreateHandle[cellType: cellType, flattenCellType: RTCoreUtil.defaultFlatten, libName: libName, designRules: rules, decoration: extractMode.decoration];

CoreProperties.PutCellTypeProp[cellType, SC.handleAtom, handle];

SC.InitialPlace[handle, RTCoreUtil.GetCoreIntProp[cellType, SC.numRows, 0]];

SCUtil.WriteTWFiles[handle: handle];

IF TWOps.TWIt[handle.name, TRUE]#NIL THEN SC.Error[callingError, Rope.Cat["Problem on Unix Placement Server. Check file ", handle.name, ".out"]];

SCUtil.ReadTWPlace[handle: handle];

SC.InitialPlace[handle, RTCoreUtil.GetCoreIntProp[cellType, SC.numRows, 0]];

-- initialResult ← SC.SAInitialPlace[handle, widthFactor];

-- saParms ← SC.SAGetParms[handle, initialResult, cellType];

-- SC.SAPlaceImprove[handle: handle, saParms: saParms, widthFactor: widthFactor];

-- SC.PlaceImprove[handle: handle, maxCycles: 1];

SC.GlobalRoute[handle];

-- SC.PlaceImprove[handle: handle, maxCycles: 1];

SC.PosImproveWL[handle, 1];

SC.OrientImproveWL[handle, 1];

SC.PosImprove[handle, 1];

SC.OrientImprove[handle, 1];

-- SCSmash.CheckFts[handle];

-- SCSmash.CheckExits[handle];

-- SC.FTImprove[handle, 10];

result ← SC.DetailRoute[handle];

RETURN[result.object]};

StandardCellDecorate: PUBLIC PWCore.DecorateProc = {

PROC [cellType: CellType, obj: Object];

SmashPins: PROC [wire: Core.Wire] = {CoreGeometry.PutPins[extractMode.decoration, wire, NIL]};

call back proc to map wires to labels

WireToLabels: PROC [wire: Core.Wire] RETURNS [LIST OF Route.Label] ~ {

net: SCPrivate.Net ← SCUtil.FindNetByWire[handle, wire];

RETURN[IF net.numberOfRegions > 0 THEN LIST[net.name] ELSE net.brokenNets]};

call back proc to order objects

ComparePos: PROC [pos1, pos2: CD.Position] RETURNS [BOOL] ~ {

IF pos1.y = pos2.y THEN RETURN[pos1.x < pos2.x]

ELSE RETURN[pos1.y < pos2.y]};

call back proc to order cellTypes

CompareCT: CoreRoute.CompareFlatCTProc ~ {

PROC [root: Core.CellType, flatCT1, flatCT2: CoreFlat.FlatCellTypeRec] RETURNS [BOOL];

flatName1: Rope.ROPE ← CoreFlat.CellTypePathRope[root, flatCT1];

instance1: SCPrivate.Instance ← SCUtil.FindInstance[handle, flatName1];

flatName2: Rope.ROPE ← CoreFlat.CellTypePathRope[root, flatCT2];

instance2: SCPrivate.Instance ← SCUtil.FindInstance[handle, flatName2];

IF instance1.curRow = instance2.curRow THEN RETURN[instance1.curPos < instance2.curPos]

ELSE RETURN[instance1.curRow < instance2.curRow]};

handle: SC.Handle ← NARROW[CoreProperties.GetCellTypeProp[cellType, SC.handleAtom]];

CoreOps.VisitRootAtomics[cellType.public, SmashPins];

IF handle # NIL THEN {

CoreRoute.DecorateRoutedArea[cellType: cellType, obj: obj, wireToLabels: WireToLabels, comparePos: ComparePos, compareCT: CompareCT];

SC.Destroy[handle]}};

Puts on public wires their side as a property

StandardCellAttibutes: PUBLIC PWCore.AttributesProc = {-- [cellType: Core.CellType]

FindSideForEachPin: CoreGeometry.EachWirePinProc = {

[wire: Core.Wire, instance: CD.Instance, min: INT, max: INT, side: CoreGeometry.Side, layer: CD.Layer] RETURNS [quit: BOOL ← FALSE]

PushPropOnAtomic: PROC [wire: Core.Wire] ~ {

sideVal: REF ANY ← CoreProperties.GetWireProp[wire, SC.sideProp];

positionVal: REF ANY ← CoreProperties.GetWireProp[wire, SC.positionProp];

CoreProperties.PutWireProp[wire, SC.sideProp, IF sideVal=NIL THEN ref ELSE sideVal];

CoreProperties.PutWireProp[wire, SC.positionProp, IF positionVal=NIL THEN NEW[INT ← min] ELSE positionVal]};

ref: REF ← SELECT side FROM

bottom => SC.bottomSideValue,

top => SC.topSideValue,

right => SC.rightSideValue,

left => SC.leftSideValue,

ENDCASE => SC.noSideValue;

IF wire.size=0 THEN PushPropOnAtomic[wire]

ELSE CoreOps.VisitRootAtomics[wire, PushPropOnAtomic]};

decoration: CoreGeometry.Decoration ← Sisyph.mode.decoration;

IF CoreGeometry.HasObject[decoration, cellType] THEN {

[] ← CoreGeometry.EnumerateWireSides[decoration, cellType, FindSideForEachPin];

EXIT};

IF cellType.class.recast = NIL THEN EXIT;

cellType ← CoreOps.Recast[cellType]

ENDLOOP};

SCLayoutAtom: ATOM ← PWCore.RegisterLayoutAtom[$SC, StandardCellLayout, StandardCellDecorate, StandardCellAttibutes];

SCPlaceAtom: ATOM ← PWCore.RegisterLayoutAtom[$SCPlace, StandardCellPlace, StandardCellDecorate, StandardCellAttibutes];

SCRouteAtom: ATOM ← PWCore.RegisterLayoutAtom[$SCRoute, StandardCellRoute, StandardCellDecorate, StandardCellAttibutes];

SCTWAtom: ATOM ← PWCore.RegisterLayoutAtom[$SCRemote, StandardCellLayoutTW, StandardCellDecorate, StandardCellAttibutes];

technologyKey: ATOM ← $cmosB; -- $cmosA or $cmosB

libName: Rope.ROPE ← "CMOSB";

extractMode: Sinix.Mode ← PWCore.extractMode;

Properties

handleAtom: PUBLIC ATOM ← CoreProperties.RegisterProperty[$SCHandle];

numRows: PUBLIC ATOM ← $numRows;

Used to specify the number of rows for a standard cell assembly. Should be a property on Core cellType being laid out

sideProp: PUBLIC ATOM ← $Side;

bottomSideValue: PUBLIC ATOM ← $bottom;

rightSideValue: PUBLIC ATOM ← $right;

topSideValue: PUBLIC ATOM ← $top;

leftSideValue: PUBLIC ATOM ← $left;

noSideValue: PUBLIC ATOM ← $none;

Used to specify the side on which a public pin is to be placed. sideProp with (mumble)Value should be a property/value on a public wire

rowProp: PUBLIC ATOM ← $Row;

Used to specify the row on which a logic cell is to be placed. rowProp and and integer row number should be a property/value on a logic cell instance

positionProp: PUBLIC ATOM ← $Position;

Used to specify the position of a logic within a row or of an public pin on a side. May be used on public wire or a logic cell instance.

usePublicPositionsProp: PUBLIC ATOM ← $UsePublicPositions;

Used to specify the position of a public in the schematic is to be retained int the layout

investmentProp: PUBLIC ATOM ← $Investment;

veryLongValue: PUBLIC ATOM ← $veryLong;

longValue: PUBLIC ATOM ← $long;

mediumValue: PUBLIC ATOM ← $medium;

shortValue: PUBLIC ATOM ← $short;

veryShortValue: PUBLIC ATOM ← $veryShort;

Used to specify the investment to make in placement.

t0SA: PUBLIC ATOM ← $t0SA;

maxTStepSA: PUBLIC ATOM ← $maxTStepSA;

lambdaSA: PUBLIC ATOM ← $lambdaSA;

tableSizeSA: PUBLIC ATOM ← $tableSizeSA;

limitSA: PUBLIC ATOM ← $limitSA;

Used to specify simulated aneealing partameters to be used for placement

widthFactorProp: PUBLIC ATOM ← $widthFactor;

bottomMaxExits: PUBLIC ATOM ← $BottomMaxExits;

rightMaxExits: PUBLIC ATOM ← $RightMaxExits;

topMaxExits: PUBLIC ATOM ← $TopMaxExits;

leftMaxExits: PUBLIC ATOM ← $LeftMaxExits;

Used to specify the maximum number or publics on a side.

bottomExitSpacing: PUBLIC ATOM ← $BottomExitSpacing;

rightExitSpacing: PUBLIC ATOM ← $RightExitSpacing;

topExitSpacing: PUBLIC ATOM ← $TopExitSpacing;

leftExitSpacing: PUBLIC ATOM ← $LeftExitSpacing;

Used to specify the HINT for publics spacing on a side.

interestingProperties: PUBLIC RTCoreUtil.PropertyKeys ← NEW[RTCoreUtil.PropertyKeysRec[20]];

Cedar does not allow initialization of a sequence in the NEW!

interestingProperties.p[0] ← SC.sideProp;

interestingProperties.p[1] ← SC.rowProp;

interestingProperties.p[2] ← SC.positionProp;

interestingProperties.p[3] ← SC.numRows;

interestingProperties.p[4] ← SC.bottomMaxExits;

interestingProperties.p[5] ← SC.rightMaxExits;

interestingProperties.p[6] ← SC.topMaxExits;

interestingProperties.p[7] ← SC.leftMaxExits;

interestingProperties.p[8] ← SC.bottomExitSpacing;

interestingProperties.p[9] ← SC.rightExitSpacing;

interestingProperties.p[10] ← SC.topExitSpacing;

interestingProperties.p[11] ← SC.leftExitSpacing;

interestingProperties.p[12] ← SC.investmentProp;

interestingProperties.p[13] ← SC.t0SA;

interestingProperties.p[14] ← SC.maxTStepSA;

interestingProperties.p[15] ← SC.lambdaSA;

interestingProperties.p[16] ← SC.tableSizeSA;

interestingProperties.p[17] ← SC.limitSA;

interestingProperties.p[18] ← SC.widthFactorProp;

interestingProperties.p[19] ← SC.usePublicPositionsProp;

Used to specify all the properties that are interesting to SC