<> <> <> <> DIRECTORY Core, CoreFlat, Ports, Rope; Combinatorial: CEDAR DEFINITIONS = BEGIN <> <> <> <> <> <> <> <> <> <> <> <> IsCombinatorial: PROC [cell: Core.CellType] RETURNS [BOOL]; <> IsNonCombinatorial: PROC [cell: Core.CellType] RETURNS [BOOL]; <> NotCombinatorial: ERROR [cell: Core.CellType]; <> <> WireType: TYPE = {input, output, gnd, vdd}; EnumerateTypedWires: PROC [cc: Core.CellType, each: PROC [Core.Wire, ROPE, WireType] RETURNS [quit: BOOL _ FALSE]] RETURNS [quit: BOOL]; <> <> <> <<>> GetTypedWires: PROC [cc: Core.CellType, type: WireType] RETURNS [Core.Wires]; <> <> <> <<>> GetWireType: PROC [cc: Core.CellType, wire: Core.Wire] RETURNS [type: WireType]; <> <> <<>> PutOutput: PROC [wire: Core.Wire, expr: ROPE]; <> <<>> GetOutput: PROC [wire: Core.Wire] RETURNS [ROPE _ NIL]; <> <> ROPE: TYPE = Rope.ROPE; ParseTree: TYPE = REF; -- Union of ROPE (for variables), REF ParseOperRec and REF INT ParseTrees: TYPE = LIST OF ParseTree; ParseOperRec: TYPE = RECORD [oper: ROPE, params: ParseTrees]; <<>> Oper: PROC [oper: ROPE, params: ParseTrees] RETURNS [ParseTree]; Not: PROC [tree: ParseTree] RETURNS [ParseTree]; And: PROC [trees: ParseTrees] RETURNS [ParseTree]; Or: PROC [trees: ParseTrees] RETURNS [ParseTree]; And2: PROC [tree1, tree2: ParseTree] RETURNS [ParseTree]; Or2: PROC [tree1, tree2: ParseTree] RETURNS [ParseTree]; <> IncorrectExpression: ERROR [expr, msg: ROPE]; ParseExpression: PROC [expr: ROPE] RETURNS [tree: ParseTree]; <> <<>> UnParseExpression: PROC [tree: ParseTree] RETURNS [expr: ROPE]; <<>> RenameVariables: PROC [tree: ParseTree, var: PROC [ROPE] RETURNS [ROPE]] RETURNS [ParseTree]; <<>> ParseOutput: PROC [wire: Core.Wire] RETURNS [tree: ParseTree]; <> <> <> RecastProc: TYPE = PROC [params: LIST OF REF] RETURNS [tree: ParseTree]; RegisterOperator: PROC [oper: ROPE, recast: RecastProc]; FetchOperator: PROC [oper: ROPE] RETURNS [recast: RecastProc]; Recast: PROC [ParseTree] RETURNS [ParseTree]; <> <> <> <<>> BindCombinatorial: PROC [cc: Core.CellType]; <> <<>> CheckTransistorsAgainstExpressions: PROC [cc: Core.CellType, checkXValues: BOOL _ TRUE]; <> <> CheckUnsuccessful: SIGNAL [level1, level2: Ports.Level]; <<>> <> InputOutputProblem: SIGNAL [type: ATOM, root: Core.CellType, flatWire: CoreFlat.FlatWire _ NIL]; <> MakeCombinatorial: PROC [cell: Core.CellType]; <> <> <> <<>> AttemptMakeCombinatorial: PROC [cell: Core.CellType] RETURNS [trans, ok, notOK: INT _ 0]; <> <> SplitCombinatorial: PROC [record: Core.CellType] RETURNS [split: Core.CellType]; <> <> <> <<>> END.