DIRECTORY CD, Core, CoreCreate, CoreFlat, RosemaryUser, Ports; Logic: CEDAR DEFINITIONS = BEGIN OPEN CoreCreate; logicCutSet, macroCutSet: ROPE; -- used by Rosemary fast, macro, gate, transistor: CoreFlat.CutSet; -- use those for the CutSet property Inv: PROC [buffered: BOOL _ FALSE] RETURNS [ct: CellType]; Tr2: PROC [type: ATOM] RETURNS [ct: CellType]; -- $pd, $pdw, $pu, $puw accepted Rec2V: PROC RETURNS [ct: CellType]; RecTTL: PROC RETURNS [ct: CellType]; Buffer: PROC[d: NAT] RETURNS [ct: CellType]; CKBuffer: PROC[d, numRows: NAT] RETURNS [ct: CellType]; TstDriver: PROC RETURNS [ct: CellType]; TristateI: PROC RETURNS [ct: CellType]; TristateNI: PROC RETURNS [ct: CellType]; And: PROC[n: NAT] RETURNS [ct: CellType]; Nand: PROC[n: NAT] RETURNS [ct: CellType]; Or: PROC[n: NAT] RETURNS [ct: CellType]; Nor: PROC[n: NAT] RETURNS [ct: CellType]; Xor2: PROC RETURNS [ct: CellType]; Xnor2: PROC RETURNS [ct: CellType]; A22o2i: PROC RETURNS [ct: CellType]; O22a2i: PROC RETURNS [ct: CellType]; A21o2i: PROC RETURNS [ct: CellType]; O21a2i: PROC RETURNS [ct: CellType]; Driver: PROC [d: NAT] RETURNS [ct: CellType]; InvDriver: PROC [d: NAT] RETURNS [ct: CellType]; SymDriver: PROC [d: NAT] RETURNS [ct: CellType]; FlipFlop: PROC [metaStableResistant: BOOL _ FALSE] RETURNS [ct: CellType]; FlipFlopEnable: PROC RETURNS [ct: CellType]; FlipFlopAsyncReset: PROC RETURNS [ct: CellType]; DLatch: PROC RETURNS [ct: CellType]; Storage: PROC RETURNS [ct: CellType]; RS: PROC RETURNS [ct: CellType]; MuxDN1: PROC [n: NAT] RETURNS [ct: CellType]; MuxD: PROC [n, b: NAT] RETURNS [ct: CellType]; MuxD2: PROC [b: NAT] RETURNS [ct: CellType]; MuxD4: PROC [b: NAT] RETURNS [ct: CellType]; MuxN1: PROC [n: NAT] RETURNS [ct: CellType]; Mux: PROC [n, b: NAT] RETURNS [ct: CellType]; Mux2: PROC [b: NAT] RETURNS [ct: CellType]; Mux4: PROC [b: NAT] RETURNS [ct: CellType]; InvMux: PROC [b: NAT] RETURNS [ct: CellType]; TristateBuffer : PROC [b: NAT] RETURNS [ct: CellType]; TristateBufferInv : PROC [b: NAT] RETURNS [ct: CellType]; Adder: PROC [b: NAT] RETURNS [ct: CellType]; Constant: PROC [b: NAT, v: INT] RETURNS [ct: CellType]; Comparator: PROC [b: NAT] RETURNS [ct: CellType]; EqConstant: PROC [b: NAT, v: INT] RETURNS [ct: CellType]; DecoderS: PROC [a: NAT, s: NAT _ 0] RETURNS [ct: CellType]; Decoder: PROC [a: NAT, s: NAT _ 0] RETURNS [ct: CellType]; Register: PROC [b: NAT] RETURNS [ct: CellType]; RegisterR: PROC [b: NAT] RETURNS [ct: CellType]; RegisterSimple: PROC [b: NAT] RETURNS [ct: CellType]; CounterCLG: PROC [n: NAT] RETURNS [ct: CellType]; CounterUp: PROC [b: NAT] RETURNS [ct: CellType]; CounterUpDown: PROC [b: NAT] RETURNS [ct: CellType]; Latch: PROC [b: NAT] RETURNS [ct: CellType]; ReverseBits: PROC [b: NAT] RETURNS [public: Core.Wires]; Transpose: PROC [b, w: NAT] RETURNS [public: Core.Wires]; Interleave: PROC [b: NAT] RETURNS [public: Core.Wires]; Ram2: PROC [b, n: NAT, sameSide, short: BOOL _ FALSE] RETURNS [ct: CellType]; Oracle: PROC [in, out, name: ROPE, log: BOOL _ FALSE] RETURNS [ct: CellType]; SetOracleFileName: PROC [id, fileName: ROPE]; GetOracleFileName: PROC [id: ROPE] RETURNS [fileName: ROPE]; WaveForm: PROC [val: ROPE, freq: NAT, firstEdge: INT] RETURNS [ct: CellType]; ClockGen: PROC [up, dn, firstEdge: INT, initLow: BOOL] RETURNS [ct: CellType]; Stop: PROC [] RETURNS [ct: CellType]; PullUp: PROC [n: NAT] RETURNS [ct: CellType]; RunRosemary: PROC [cellType: CellType, design: CD.Design, cutSet: CoreFlat.CutSet _ NIL] RETURNS [tester: RosemaryUser.Tester]; Counter: PROC [b: NAT] RETURNS [ct: CellType]; ShiftReg: PROC [b: NAT] RETURNS [ct: CellType]; END.  Logic.mesa Copyright Σ 1986, 1987 by Xerox Corporation. All rights reserved. Last Edited by: Louis Monier October 28, 1987 11:58:35 am PST Bertrand Serlet March 30, 1987 10:34:12 pm PST Jean-Marc Frailong December 8, 1987 2:25:00 pm PST Pradeep Sindhu July 20, 1987 2:28:08 pm PDT This module provides the basic blocks for logic description and simulation of ICs. Every procedure corresponds to an icon in the library "Logic.dale"; extracting such an icon with Sisyph calls the corresponding procedure. The difference with a library like SSI is that there is no electrical notion attached to the cells, only logic behavior. There are two types of cells in this library: the simple ones and the composite ones. Simple ones (inverter, nor4, ...) are similar to the cells in SSI and correspond to a single standard cell in most decent libraries. The composite ones (i.e. adder, counter) have a Core structure using cells of the first type as leaves, or a very specific layout (RAM, ROM, PLA). All types have a behavioral procedure for logic simulation using Rosemary. CutSets for simulation fast collects all known simulation accelerators into a single cutset and need to be changed when new cutsets are added macro enables only Logic macros and basic gates gate enables only Logic basic gates (warning, very slow...) transistors is in fact NIL, so everything is at transistor level except unimplemented celltypes Very basic standard cells "Vdd", "Gnd", "I", "X" "Vdd", "Gnd", "I", "X" "Vdd", "Gnd", "I", "X", "Vth" "Vdd", "Gnd", "I", "X" "Vdd", "Gnd", "I", "X" "Vdd", "Gnd", "I", "X" "Vdd", "Gnd", "I", "X", "EN", "NEN" "Vdd", "Gnd", "I", "X", "EN" "Vdd", "Gnd", "I", "X", "EN" "Vdd", "Gnd", Seq["I", n] "X" "Vdd", "Gnd", Seq["I", n] "X" "Vdd", "Gnd", Seq["I", n] "X" "Vdd", "Gnd", Seq["I", n] "X" "Vdd", "Gnd", "I-A", "I-B", "X" "Vdd", "Gnd", "I-A", "I-B", "X" "Vdd", "Gnd", "A", "B", "C", "D" ,"X" "Vdd", "Gnd", "A", "B", "C", "D" ,"X" "Vdd", "Gnd", "A", "B", "C" ,"X" "Vdd", "Gnd", "A", "B", "C" ,"X" "Vdd", "Gnd", "I", "X" "Vdd", "Gnd", "I", "nX" "Vdd", "Gnd", "I", "X", "nX" "Vdd", "Gnd", "D", "Q", "NQ", "CK" "Vdd", "Gnd", "D", "Q", "NQ", "CK", "en", "nEn" "Vdd", "Gnd", "D", "Q", "NQ", "CK", "r" "Vdd", "Gnd", "D", "Q", "S" Not standard cells, but basic cells anyway "Vdd", "Gnd", "bit", "nbit" "Vdd", "Gnd", "R", "S", "Q", "nQ" Multiplexers "Vdd", "Gnd", Seq["Select", n], Seq["In", n], "Output" "Vdd", "Gnd", Seq["Select", n], Seq["In", n, Seq[size: b]], Seq["Output", b] "Vdd", "Gnd", "Select0", "Select1", Seq["In0", b], Seq["In1", b], Seq["Output", b] "Vdd", "Gnd", "Select0", "Select1", "Select2", "Select3", Seq["In0", b], Seq["In1", b], Seq["In2", b], Seq["In3", b], Seq["Output", b] "Vdd", "Gnd", Seq["Select", s], Seq["In", n], "Output", with s=NbBits[n] "Vdd", "Gnd", Seq["Select", s], Seq["In", n, Seq[size: b]], Seq["Output", b] where s=NbBits[n] "Vdd", "Gnd", "Select", Seq["In0", b], Seq["In1", b], Seq["Output", b] "Vdd", "Gnd", Seq["Select", 2], Seq["In0", b], Seq["In1", b], Seq["In2", b], Seq["In3", b], Seq["Output", b] "Vdd", "Gnd", "Select", Seq["In0", b], Seq["In1", b], Seq["nOut", b] Tri-state Buffers "Vdd", "Gnd", Seq["Input", b], Seq["Output", b], "enable" "Vdd", "Gnd", Seq["Input", b], Seq["Output", b], "enable" Arithmetic "Vdd", "Gnd", "carryIn", Seq["A", b], Seq["B", b], Seq["Sum", b], "carryOut" Output is formed an Vdd and Gnd conections to generate the required constant pattern "Vdd", "Gnd", Seq["A", b], Seq["B", b], "AEqB" "Vdd", "Gnd", Seq["In", b], "out" "Vdd", "Gnd", Seq["Address", a], Seq["Select", s], with s=0 => s _ 2**a "Vdd", "Gnd", Seq["Address", a], Seq["Select", s], "Enable", with s=0 => s _ 2**a Macros with states "Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b], Seq["nOutput", b], "en" "Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b], Seq["nOutput", b], "en", "r" "Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b], Seq["nOutput", b] PIn[n], nCOut[n], CIn, COut (of the counter, enabled by CIn) Carry lookahead generation for a counter (tree). Naive users, beware... "Vdd", "Gnd", "Load", "Count", "Cin", "Cout", "CK", Seq["Input", b], Seq["Output", b], Seq["nOutput", b]. Load has priority over Count. Uses a carry-lookahead scheme. "Vdd", "Gnd", "Load", "Up", "Down", "Cin", "Cout", "Bin", "Bout", "CK", Seq["Input", b], Seq["Output", b], Seq["nOutput", b] (Bin, Bout are the borrow signals). Load has priority over Up and Down. If both Up and Down are set, results in NoOp. Uses a carry-lookahead scheme. "Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b] Useful wire icons Reverse the order of the bits of a b-bit bus Transform a bus of w words of b bits into a bus of b words of w bits "wSide" has w words of b bits, "bSide" has b words of w bits Interleave 2 buses of b bits into a single bus of 2*b bits "Even[b]", "Odd[b]", "Result[2*b]" Result[2*i]=Even[i], Result[2*i+1]=Odd[i] Standard generators "Vdd", "Gnd", Seq["Input", b], Seq["Output", b], Seq["RAdr", a], Seq["WAdr", a], "enW" Fifo: PROC [b, n, nbFreeNF: NAT] RETURNS [ct: CellType]; "Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b], "Load", "UnLoad", "Reset", "DataAv", "Full", "NF" For the custom block: "Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b], "Read", "Write", "Reset" For Rosemary simulation only (no layout) "In", "Out", "CK" Disagreement: SIGNAL [shouldBe, is: Ports.Level, oracleName: ROPE, index: CARD]; -- see in Ports "RosemaryLogicTime", "Out" Default values on icon: freq_2, firstEdge_1 "RosemaryLogicTime", "Clock" Default values on icon: up_dn_firstEdge_1; initLow_TRUE raises an error when its input "ShouldBeFalse" is true If the cutset passed is defaulted to NIL, then get it from the $Simulation celltype property: $Fast => macro level, $Transistors=transistor level, otherwise gate level. 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