StdCellsCmosBDoc.tioga
Copyright Ó 1987 by Xerox Corporation. All rights reserved.
Last Edited by: Louis Monier August 24, 1986 1:08:38 am PDT
Bertrand Serlet March 30, 1987 10:39:15 pm PST
Follows a minimal documentation of the CMosB standard cell library. All times are typical. The typical input load (one n-tr plus one p-tr, standard sizes), equal to F=0.17 pF. The format is:
name of cell (as used by Logic), name of ChipNDale object (.sch and .mask)
width of the cell, in number of tracks, each worth 10m (the height is fixed at 104m)
fall and rise time (when applicable), worse case from input to output.
gnd, C2GD00A, width=1
inv, C2IV00A, width=2 Tr(ns)=0.7*F Tf(ns)=0.5*F
invBuffer, C2IV00B, width=3 Tr(ns)=0.4*F Tf(ns)=0.3*F
tstDriver, C2BD02A, width=5 Tr(ns)=0.9*F + 0.3 Tf(ns)=0.7*F + 0.2
and2, C2AN02A, width=4 Tr(ns)=0.7*F + 1.3 Tf(ns)=0.5*F + 1.2
and3, C2AN03A, width=5 Tr(ns)=0.7*F + 2.5 Tf(ns)=0.5*F + 1.2
and4, C2AN04A, width=6 Tr(ns)=0.7*F + 3.5 Tf(ns)=0.5*F + 1.2
nand2, C2NA02A, width=3 Tr(ns)=0.7*F + 0.5 Tf(ns)=1.0*F + 0.3
nand3, C2NA03A, width=4 Tr(ns)=0.7*F + 0.5 Tf(ns)=1.5*F + 1.0
nand4, C2NA04A, width=5 Tr(ns)=0.7*F + 0.5 Tf(ns)=2.0*F + 1.5
or2, C2OR02A, width=4 Tr(ns)=0.7*F + 1.0 Tf(ns)=0.5*F + 2.4
or3, C2OR03A, width=5 Tr(ns)=0.7*F + 1.0 Tf(ns)=0.5*F + 4.5
or4, C2OR04A, width=6 Tr(ns)=0.7*F + 1.0 Tf(ns)=0.5*F + 6.5
nor2, C2NO02A, width=3 Tr(ns)=1.5*F + 0.9 Tf(ns)=0.5*F + 0.5
nor3, C2NO03A, width=4 Tr(ns)=2.0*F + 2.5 Tf(ns)=0.5*F + 0.5
nor4, C2NO04A, width=5 Tr(ns)=3.0*F + 3.5 Tf(ns)=0.5*F + 0.5
xnor2, C2XN02A, width=6
a2202i, a2202i, width=5
o22a2i, o22a2i, width=5
a21o2i, a21o2i, width=4
ff, ff, width=12
Quick and very dirty estimates: an average wiring capacitance will be 1*F for small and medium chips, 2*F for large chips. If you insist in keeping a number in mind, though it absolutely does not make sense, one simple gate is worth 2ns and a complex one 4ns. For flip-flops, the set-up time is 2ns, the hold time -1.5 ns, and clock to outputs is 3ns for a fan-out of 1.