[_CD4_]<datools7.0>CellLibraries>StdCellsCmosB.mesa!7

StdCellsCmosB.mesa

Louis Monier, July 14, 1986 1:25:29 pm PDT

Bertrand Serlet June 4, 1987 11:57:13 pm PDT

Louis Monier October 26, 1987 2:38:07 pm PST

Defines every cell of a standard cell library for CMosB (2m CMOS with two levels of metal, fabricated by both VTI and ICL). Will be used by the library "Logic".

DIRECTORY

CD, Core, CoreDirectory, CoreGeometry, CoreOps, CoreProperties, LogicUtils, PWCore, RefTab, Rope, SymTab;

StdCellsCmosB: CEDAR PROGRAM

IMPORTS CoreDirectory, CoreGeometry, CoreOps, CoreProperties, LogicUtils, PWCore, RefTab, Rope, SymTab

~ BEGIN

Library Layout Atom

GetMask: PROC [cellType: Core.CellType] RETURNS [mask: Core.CellType] = {

mask ← LogicUtils.LibraryGet[

NARROW [CoreProperties.GetCellTypeProp[cellType, $Library]],

Rope.Cat[CoreOps.GetCellTypeName[cellType], ".mask"]

];

};

LayoutLibrary: PWCore.LayoutProc = {

obj ← CoreGeometry.GetObject[PWCore.extractMode.decoration, GetMask[cellType]];

};

DecorateLibrary: PWCore.DecorateProc = {

extractedCT: Core.CellType ← GetMask[cellType];

extractedToSource: RefTab.Ref ← RefTab.Create[extractedCT.public.size];

FindInExtractedPublic: CoreOps.EachWireProc = {

FOR names: LIST OF Rope.ROPE ← CoreOps.GetFullWireNames[cellType.public, wire], names.rest WHILE names#NIL DO

name: Rope.ROPE ← names.first;

extractedWire: Core.Wire ← CoreOps.FindWire[extractedCT.public, name];

previousSourceWire: Core.Wire ← NARROW [RefTab.Fetch[extractedToSource, extractedWire].val];

IF extractedWire=NIL OR extractedWire.size#0 THEN LOOP;

IF previousSourceWire#NIL AND previousSourceWire#wire THEN SIGNAL PWCore.PinsCorrespondingToSeveralPublics[cellType, obj, LIST [previousSourceWire, wire], CoreGeometry.GetPins[PWCore.extractMode.decoration, extractedWire]];

IF NOT CoreGeometry.HasPins[PWCore.extractMode.decoration, extractedWire]

THEN SIGNAL PWCore.NoPinsOnAtomicPublic[cellType, obj, extractedWire, name];

CoreGeometry.AddIndirectLazyPins[PWCore.extractMode.decoration, wire, extractedWire];

[] ← RefTab.Store[extractedToSource, extractedWire, wire];

ENDLOOP;

};

[] ← CoreOps.VisitWire[cellType.public, FindInExtractedPublic];

};

Preparation

library: CoreDirectory.Library ← SymTab.Create[];

Adding in the Library

schLibrary: Rope.ROPE = "SCLibCMOSBSch";

maskLibrary: Rope.ROPE = "SCLibCMOSBMask";

MakeSCCell: PROC [name, schName: Rope.ROPE] ~ {

sch: Core.CellType ← LogicUtils.LibraryGet[schLibrary, schName];

PWCore.SetLayout[sch, $GetLibrary, $Library, maskLibrary];

[] ← CoreDirectory.Insert[library, name, sch];

};

[] ← PWCore.RegisterLayoutAtom[$GetLibrary, LayoutLibrary, DecorateLibrary];

Needed by the router

MakeSCCell["feedthru", "feedthru.sch"];

Basic combinatorial cells

MakeSCCell["gnd", "gnd.sch"];

MakeSCCell["vdd", "vdd.sch"];

MakeSCCell["inv", "inv.sch"];

MakeSCCell["invBuffer", "invBuffer.sch"];

MakeSCCell["tstDriver", "tstDriver.sch"];

MakeSCCell["rec2V", "rec2V.sch"];

MakeSCCell["recTTL", "recTTL.sch"];

MakeSCCell["and2", "and2.sch"];

MakeSCCell["and3", "and3.sch"];

MakeSCCell["and4", "and4.sch"];

MakeSCCell["nand2", "nand2.sch"];

MakeSCCell["nand3", "nand3.sch"];

MakeSCCell["nand4", "nand4.sch"];

MakeSCCell["or2", "or2.sch"];

MakeSCCell["or3", "or3.sch"];

MakeSCCell["or4", "or4.sch"];

MakeSCCell["nor2", "nor2.sch"];

MakeSCCell["nor3", "nor3.sch"];

MakeSCCell["nor4", "nor4.sch"];

MakeSCCell["xor2", "xor2.sch"];

MakeSCCell["xnor2", "xnor2.sch"];

MakeSCCell["a22o2i", "a22o2i.sch"];

MakeSCCell["o22a2i", "o22a2i.sch"];

MakeSCCell["a21o2i", "a21o2i.sch"];

MakeSCCell["o21a2i", "o21a2i.sch"];

MakeSCCell["pd", "pd.sch"];

MakeSCCell["pu", "pu.sch"];

MakeSCCell["pdw", "pdw.sch"];

MakeSCCell["puw", "puw.sch"];

Flip-flops and Latches

MakeSCCell["ff", "ff.sch"];

MakeSCCell["ffEn", "ffEn.sch"];

MakeSCCell["dLatch", "dLatch.sch"];

Registration

[] ← CoreDirectory.RegisterLibrary[library, "CMOSB"];

END.