<> <> <> <> <> <<>> DIRECTORY Core, CoreCreate, Rosemary, Sisyph; SSI: CEDAR DEFINITIONS = BEGIN OPEN CoreCreate; <<>> <> <<>> <<"Vdd", "Gnd", "Input", "nOutput">> Inverter: PROC [nw: NAT _ 4, nl: NAT _ 2, r: REAL _ 2.5, pw: NAT _ 0, pl: NAT _ 2, size: Rosemary.TransistorSize _ drive] RETURNS [ct: CellType]; <<>> <<"Vdd", "Gnd", "Input", "Drive", "nDrive", "nOutput">> TristateBuffer: PROC [nw: NAT _ 4, nl: NAT _ 2, r: REAL _ 2.5, pw: NAT _ 0, pl: NAT _ 2] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Input", i], "nOutput">> NAnd: PROC [i: NAT _ 2, nw: NAT _ 4, nl: NAT _ 2, r: REAL _ 2.5, pw: NAT _ 0, pl: NAT _ 2] RETURNS [ct: CellType]; NAnd2: PROC [nw: NAT _ 4, nl: NAT _ 2, r: REAL _ 2.5, pw: NAT _ 0, pl: NAT _ 2] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Input", i], "Output">> And: PROC [i: NAT _ 2, nw: NAT _ 4, nl: NAT _ 2, r: REAL _ 2.5, pw: NAT _ 0, pl: NAT _ 2] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Input", i], "nOutput">> NOr: PROC [i: NAT _ 2, nw: NAT _ 4, nl: NAT _ 2, r: REAL _ 2.5, pw: NAT _ 0, pl: NAT _ 2] RETURNS [ct: CellType]; NOr2: PROC [nw: NAT _ 4, nl: NAT _ 2, r: REAL _ 2.5, pw: NAT _ 0, pl: NAT _ 2] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Input", i], "Output">> Or: PROC [i: NAT _ 2, nw: NAT _ 4, nl: NAT _ 2, r: REAL _ 2.5, pw: NAT _ 0, pl: NAT _ 2] RETURNS [ct: CellType]; END.