LogicDoc.tioga
Copyright Ó 1987 by Xerox Corporation. All rights reserved.
Louis Monier, July 29, 1986 12:06:00 pm PDT
Last Edited by: Louis Monier October 13, 1987 10:55:16 am PDT
Bland, September 30, 1987 3:06:34 pm PDT
Jean-Marc Frailong September 17, 1987 1:27:08 am PDT
Bertrand Serlet March 30, 1987 10:22:40 pm PST
Logic Library
CEDAR 7.0 — FOR INTERNAL XEROX USE ONLY
Logic Library
Louis Monier
Abstract: The "Logic" library is a set of icons representing the most common SSI and MSI blocks (simple gates, adder, register file, ...). Each icon is associated with a behavioral model (a simulation Rosemary procedure) and at least one layout generation procedure, either through a standard cell representation or standard generator.
Created by: Louis Monier
Maintained by: Louis Monier <Monier.pa>
Keywords: Logic Simulation, Icon, Schematic, Sisyph, Rosemary, Standard Cells
XEROX   Xerox Corporation
    Palo Alto Research Center
    3333 Coyote Hill Road
    Palo Alto, California 94304

For Internal Xerox Use Only
1. Introduction
Generalities
The "Logic" library is intended to be used for drawing schematics at a logic level. Each icon comes with a simulation procedure, and either a standard cell decomposition or a standard generator.
All schematics must be drawn in the CMosB technology of ChipNDale, using the comment layer for wires. The menus SPACE-O and SPACE-P contain most of the commands you need. The font Helvetica8 (4/8) is a good one for text.
(*) means I am working on it.
What is public
The icons in the "released" box are public. The name, size, shape of the icon, the position of the pins, and the general semantic are supposed to be stable, i.e. any change will be done with profuse apologies and a lot of advance notice.
What is not public
Anything else in the library, the implementation of Logic, the name of the public wires of an icon, the layout of the standard cells, the notion of time in Rosemary, are all subject to change, and in fact do change all the time to track updates in the DA system, user feedback, performance tuning, ... Do not rely on anything at this level.
What you need to know before starting
You should be familiar with ChipnDale, Sisyph, and Rosemary. Understand icons, structured wires, satellites, ... If the documentation is not sufficient, complain to the author/maintainer.
[Artwork node; type 'ArtworkInterpress on' to command tool]
Bus descriptor, wire extractor, range extractor and composer
For composite wires, you should know about the generators put out by Bertrand Serlet (see above). P-middle is the commands to access Composer, Extractor, Range Extractor, and Bus Constructor. As usual, 0 is the high-order bit (wire) and is indicated by an extra-wide pin in the composer. Never, never, never, attempt to edit such icons.
Starting up
Bringover everything (% BringDATools) and start everything (% Schematics.load). Read in your design (% CDRead MyChip.dale) and, unless you know the library by heart, read also the library (% CDRead Logic.dale). Before you start doing any real work, you can play with the design "TestLogic.dale" as a model.
Now import the icons that you need from "Logic" into your design (cf. ChipNDale documentation to do imports): the copy command to import a cell is the best because you don't have to know the name of the icon, just to point at it. Start drawing!
The library
Information about timing and size will be provided for every cell and macro (*). All cells have a fixed height of 104m. The width is a multiple of 10m called here a track. Input loads are counted in standard loads (= 0.2pF) and output drives in standard drives (= drive of an inverter, i.e. a 2/20 n-device and a 2/50 p-device). All these numbers are subject to changes.
Simulation
For large simulations involving a simulation proc and a test proc, refer to the Rosemary documentation (available only in Basque and Southern Mongolian through Rick Barth, Unlimited Doc. Inc., rm 2218).
For interactive simulation, build a cell including the cell(s) to be tested with testing paraphernalia (roseClock.icon among them). Vdd and Gnd get their value automatically. Beware that the three logic level L, X, and H are used, and that all states are initialized to X.
Which wires do you want to display? Here are the possibilities:
- Every top-level named wires (i.e. part of the internal wire of the top cell) will be displayed. A wire is named if you name it explicitely or if the inherited names do not conflict.
- Using the add command in the Rosemary typescript, you can add to the timing display (oscilloscope) any wire which you can access by name. Familiarity with the commands available in the Rosemary typescript and long-name syntax will help a lot.
Now you can simulate at two different levels. Most macros come with a behavioral procedure which tries hard to reproduce reality, and a decomposition in more primitive cells. The behavioral model of basic cells has been checked and can be reasonably be trusted. The default uses only the basic cells: it is thus slow but quite precise. If you are worried about speed, you can add in the simulation cell an object satellite [Simulation: $Fast] to use top-level behavioral procedures: faster, but not as safe.
Then call "Sisyph Extract and Rosemary" in the SPACE-O menu; your cell will be extracted, Rosemary will create a simulation and a display panel with a typescript and an oscilloscope-like display. If instead you get an error window with no message on the terminal, come and complain for this should not happen.
Start the simulation by bugging "Single Eval" and watch the values on the ports change; for faster action, use "Proceed" and "Interrupt".
Clock generator
By use of sufficiently advanced technology (i.e. magic) the following notion of time is provided: everytime you bug the "single eval" button in the Rosemary panel, the time is incremented by 1.
The clock generator roseClock has access to this "time". It accepts four parameters: up, dn, firstEdge (all integers expressed in time units), and initLow, a boolean specifying the initial state of the clock. The defaults (up ← dn ← firstEdge ← 1; initLow← TRUE) provide a simple tick-tack generator: starting in a low state, it alternates between H and L everytime you bug the "single eval" button.
How to reach infinity: if you need to specify a single pulse and would like to say dn ← infinity, you can use the value LAST[INT] (=2147483647 cycles, which looks like a very long simulation), or by convention -1 will have the same effect.
Oracle
The oracle is a test procedure that is particularly useful for testing simple blocks without coding. It has three required parameters, an input bus (in), an output bus (out), and the name of the file containing test vectors (id). The Oracle's default behavior is to stop the first time it finds an error; however, if a fourth optional parameter (log) is used, the Oracle records errors and continues.
Oracle: Computational Model
On the rising edge of the oracle clock, the oracle does two things, in the order given: (1) it advances to the next line of the test vector file; and (2) it drives its outputs to values that appear on the left hand side of this line. These values stay on the output wires of the oracle till the next rising edge of the oracle clock, at which point the outputs are driven to values specified by the following line.
On the falling edge of the oracle clock, the oracle compares the values on its input wires with the values specified on the right hand side of the current line. If there is disagreement, it signals this, typically causing the simulation to enter the debugger.
Oracle: Parameters
Here are definitions for the four oracle parameters:
id: The name is used to find the default file name (id) or (id).oracle and to generate a log file as ///Temp/(id).bugs if you use the log feature.
log: If set, the log parameter will cause the oracle to dump all errors found during simulation (not during parsing) in a file ///Temp/(id).bugs instead of signaling every mismatch. This option is turned off by default.
in, out: The input and output wires are structured, and you must specify the structure of subwires by listing the size of every component. By convention, an atomic wire has size 0, while a single-element composite wires (a rare beast) has size 1. If a wire has more structure, you enclose the structure of its subwires in a pair of (), recursively without restriction on the depth of wires.
Example:
out ← "0 8 (0 32)" -- a bit, a byte, and a 32-bit bus with its parity
in ← "0 4" -- a bit and a nibble
Oracle: Standard Semantics for Files of Test Vectors
Stimuli and expected results are stored in a file, one line per "clock cycle". This means that if the circuit under test has a single stage of delay (for example a D flop), the right-hand side of a given line corresponds to the outputs that should appear if the left-hand side of the previous line were placed on the inputs one cycle earlier. Thus, the oracle file for a D flop should have the following test vectors:
 0 | x
 1 | 0
 0 | 1
 0 | 0
 1 | 0
 x | 1. (Fixed-pitch fonts were invented for this purpose. )
And, if the test circuit has two stages of delay, then the right hand side corresponds to the input two lines earlier, etc.
Here is a example of a more complex test vector:
1 FF ( 0 FF03 ) | 1 00FF 
Notice the () with spaces around them match the wire description. Now, in a case where we don't care about the single-bit wire in the result, it could be:
1 FF ( 0 FF03 ) | X 00FF 
And if we want to tristate the low-order bit of the second input wire, it would be:
1 F(111X) ( 0 FF03 ) | X 00FF 
Now the syntax:
Value ::= SimpleValue | StructuredValue
SimpleValue ::= Digit ?Digit
StructuredValue ::= ( Value ?Value )
Digit ::= 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F | X | ExpandedDigit
ExpandedDigit ::= (Level Level Level Level)
Level ::= 0 | 1 | X
Values will be converted to a sequence of levels, zero-extended, and distributed on the corresponding wire. Simple values are specified by hex digits (including X) such as 0, 1, 35, 4FFA and X022XX. Any hex digit can also be specified as four bits exactly in a pair of (), as in (0011), (001X) or (XX0X): no space inside a value! To specify the values for a deeply structured wire, use parentheses and spaces. Don't forget the spaces or the parser will get confused.
For inputs, an X on a wire means don't care; for outputs, it means tristate.
The file is read every time you click the Start button in Rosemary, so you can modify it without re-extracting. The name of this file is defaulted to (id) or (id).oracle, but you can change it with
← Logic.SetOracleFileName["TheIdName", "NewFileName"]
and if you are confused as to which file name is currently used, type
← Logic.GetOracleFileName["TheIdName"]
The Oracle: Dual Clock Method For Standard Semantics
For most circuits built using items in SCLogic, using a single clock for both oracle and circuit might work, especially if the circuits are at transistor level. However, problems arise when the test circuit has a behavioral proc. Because the single clock method does have problems, the dual clocking scheme, using one clock for the oracle and one for the circuit is recommended.
The oracle clock should have the parameters <up𡤂, dn𡤂, firstEdge𡤂>. The circuit clock should have the parameters <up𡤂, dn𡤂>. Using these parameters causes the oracle clock to be a quarter cycle delayed with respect to the circuit clock. Thus, the order of events in a given cycle is:
- circuit clock rising edge (circuit samples values just before edge and computes its outputs)
- oracle clock rising edge (oracle goes to new line and places left hand side on circuit inputs)
- circuit clock falling edge
- oracle clock falling edge (oracle checks circuit output against right hand side)
Assertion verification
The icon roseStop has the property that if its input (anywhere on its periphery) is high, then it raises a Rosemary signal. When the Event Window opens, it is possible to update the display by bugging the Update button. One can also proceed by bugging Proceed in the Event Window (not in the Rosemary panel).
Due to the algorithm used by Rosemary, non-race-free circuits can generate glitches which could raise the signal though the final value after the simulation settles would not. To avoid this, the input is sampled on the next Time transition.
Cosmetics
A family of arrows is provided. These arrows are strictly cosmetic and ignored by the extractor.
A contact cell is also provided: it is useful to indicate connections among crossing wires without having to break these wires.
Power supply
For historical reasons, there are two sets of Vdd and Gnd icons: they are now equivalent. The cells providing logic 0 and 1 are automatically inserted by the SC layout system, so don't worry about how many such symbols you use.
The Static checker
It is a good idea to run Static, the static checker, on your design. In order to avoid false errors, mark every unconnected output (for example the complementary output of a register that you do not use) with the unconnected icon, a little black square.
Layout
Finally, layout time! For every standard cell block you must have a cell including the object satellite "Layout: $SC". Public wires: if in this schematics a wire intersects a side of the cell, then the wire corresponding wire(s) in the layout will come out of the same side.
Current restrictions: a wire can be present only on one side; and if a composite wire appears in the internal of the cell, all of its atomic wires must be used (i.e. connected).
Finally poke "Extract and Layout" in the SPACE-O menu, stand back and wait.
2. Simple logic gates
Each one of these gates corresponds to a single standard cell. The "zero-th input" is specified by a thicker wire. When a gate has series transistors (e.g. nand), the zero-th input is the closest from the power supply, e.g. it is the slowest. For a description of the public wire and the parameters, refer to the interface Logic.mesa. Most gates come in two different looks (bubbles before or after).
Inverter, buffer and tristate driver
The inverter is provided with two different looks. A buffering inverter is represented by the same icons, but with a "2" inside. It has twice the transistor size of the regular inverter, but provides a smaller layout than 2 regular inverters in parallel. Input load and output drive are 1 for the inverter, 2 for the buffering inverter.
The basic tri-state driver is inverting and has complementary enables. The loads are 2 on the input, 2/3 on the negative enable, 1/3 on the enable. The output drive is 2/3.
[Artwork node; type 'ArtworkInterpress on' to command tool]
Inverters, buffer and tri-state
Simple Combinatorial Gates
You find the and, or, nand and nor gates, in 2, 3 and 4-input versions, plus xor2 and xnor2. The semantic is obvious.
[Artwork node; type 'ArtworkInterpress on' to command tool]
The simple gates, with two different looks
If any input shows X instead of a clean H or L, the gate tries hard to still produce a good output: for example and2[L, X]=L.
All input loads are unit loads, except on xor2 and xnor2, where there are double loads.
The sizes for negative gates are nor2=nand2=30m, nor3=nand3=40m, nor4=nand4=50m.
The sizes for positive gates are or2=and2=40m, or3=and3=50m, or4=and4=60m.
More Complex Combinatorial Gates
This collection will be kept to a minimum. So far, the xor2 and xnor2, and three composite gates: the 2-wide-2 AND-4 input AND-OR-inverter, also known as a22o2i, its dual o22a2i, and the a21o2i.
[Artwork node; type 'ArtworkInterpress on' to command tool]
The more complex gates
This collection will be kept to a minimum . So far, the xor2 and xnor2, and three composite gates: the 2-wide-2 AND-4 input AND-OR-inverter, also known as a22o2i, its dual o22a2i, and the a21o2i.
Input loads are all unit loads.
Sizes: xor2=xnor2=60m, a22o2i=o22a2i=50m, a21o2i=40m.
Output drives: 1/2 for all those cells.
Flip-flops
The only cell which can hold a bit of state is ff, a simple edge-triggered flip-flop with an input, a clock, and complementary outputs.
The clock is internally inverted and buffered; the load on D and CK is one unit load. Both outputs have a unit drive. The size of ff is currently 100m (*).
There is now a version of the flip-flop call ffEn with data enable which takes additional inputs en and nEn. The size of ffEn is currently 140m (*), subtantially smaller than a flip-flop with a 2-input multiplexer. This cell is used to make registers, counters and shift registers.
3. Macros
Macros are simply a convenience for the user: they implement common functions using the basic standard cells gates mentionned above. As any library, this collection of macros cannot fulfill any designer's dream, and in fact it will be kept to a minimum size to simplify maintenance. Our DA system is sufficiently open and extensible that it is staightforward with some drawing and coding to produce any desired macro. When a designer needs a macro, the right thing to do is to implement it himself, and then check if it would benefit others if the macro was incorporated in the library.
All sequential elements (register, counter, shift register) change state on the rising edge of the clock. All inputs are synchronous.
Whenever applicable, the parameters have the following names: b is the number of bits in a word, n is the number of inputs, and v is a value, usually a signed integer.
The default value b𡤀 is illegal and is used to detect icons missing a parameter specification. b<0 is of course illegal, since b is a NAT. One-bit macros (b=1) may sometimes be meaningful, but they are usually a pain because their public contain structured wires with one element, which is not the same as atomic wires. Special cases have been made for the multiplexers, and upon request, I might hack more special cases.
Inverting Buffer - Obsolete
An inverting buffer of drive d is equivalent to d inverters in parallel. This macro is now painted red and is obsolete and should be replaced by the new drivers (don't forget that the new drivers parameter is expressed in inverters to load, and thus is 4 times the parameter for the old buffer icon).
Drivers
The drivers are general-purpose composite buffers. They come in 3 flavors: inverting, direct and symmetrical. All are distinguished by a letter L inside an inverter-style icon. All drivers accept a single integer parameter d which expresses the number of inverters to be loaded with the output. The symmetrical driver produces complementary outputs with the required drive. The input load on all drivers is 1 or 2 standard inverter loads (depending on the required drive).
[Artwork node; type 'ArtworkInterpress on' to command tool]
Drivers
Simple n-inputs gates
The and, or, nand and nor gates come in n-input version.
[Artwork node; type 'ArtworkInterpress on' to command tool]
The n-input version of simple gates
For n=0, the system complains. For n=1, the system also complains, though this might change (*). For n=2, 3, 4 you get one of the standard cells mentionned above. For n>4, the following substitutions are used for the divide and conquer operation:
and -> nor2[nand]
nand -> nand2[and]
or -> nand2[nor]
nor -> nor2[or]
For example, nor[7]=nor2[or[4], or[3]].
Flip-flops with options
The ordinary flip-flop comes with several options: reset, preset, both, and enable.
[Artwork node; type 'ArtworkInterpress on' to command tool]
FLip-flops with options
All these signals are synchronous. Reset has precedence over preset and enable.
Registers
Registers are made of a sequence of flip-flops and come in three options: simple, with enable, and with enable and reset.
[Artwork node; type 'ArtworkInterpress on' to command tool]
The registers
Reset overrides enable.
TristateBuffer
Output is high impedance if enable is low, follows or complements the inputs if enable is high. There is an inverting version and a non-inverting one.
SC: The inverting buffer is a sequence of tstDriver with a single inverter to provide the complementary enable signal. Similarly, the non-inverting buffer uses a sequence of b inverters to first invert the inputs.
Adder[b]
Well, it adds. So far, only a ripple carry version is available. It is implemented as a sequence of oneBitAdder.sch, courtesy of Alfred Permuy.
[Artwork node; type 'ArtworkInterpress on' to command tool]
The adder and the ripple-carry cell
A version with full-CLA will follow (*).
Constant[b, v], Comparator[b] and EqConstant[b, v]
The output of the constant is constantly driven to a fixed b-bit value v. It is legal to specify a size larger than 32 bits as long as the value fits on 32 bits (temporary restriction *). The value is sign-extended to fill-up the b-bit word. Two's complement arithmetic is used, so [b=3, v=-1] is equivalent to [b=3, v=7].
The comparator checks whether two b-bit inputs are bit-wise equal. The constant comparator checks whether the b-bit input is equal to a specified constant v.
[Artwork node; type 'ArtworkInterpress on' to command tool]
The constant, comparator, and comparator with a constant
The constant is implemented as a bunch of wires connecting to Vdd and Gnd.
The comparator uses one xnor2 gate per pair of input bit, and the b resulting bits are run through a b-input and gate. The load on every input is 2.
The comparator with a constant can be viewed as a one-output decoder: the compare-to-zero inputs are nored, the compare-to-zero inputs are anded, and both are combined in an and2 gate. Special cases for comparing to all zeros (a nor gate) and all ones (an and gate) are provided.
Multiplexers[n, b]
There are really a lot of multiplexers, four families exactly: encoded versus decoded select lines, and 1-bit or b-bit (bus) versions. In addition, special icons (and sometimes different implementations) are provided for 2, (3) and 4 inputs. The number of inputs is denoted by n, and the size of the buses is b.
[Artwork node; type 'ArtworkInterpress on' to command tool]
The dynasty of the multiplexers
Decoded muxes all have n select lines and n inputs. The generic 1-bit n-input mux is made of n tristate drivers followed by a single inverter. The b-bit version is obtained by replicating b times the 1-bit version and adding suitable buffers (*) on the select lines. Special cases for n=2 (complex gate a22o2i followed by an inverter), and n=3, 4 (two levels of nand gates).
At most one select line must be high in order to select an input. The usual convention of numbering wires applies and select line i selects the i-th input. Out of this envelop, the value of the output depends on the implementation, and no assumption should be made; however, for curious types, the current implementation is:
All select lines low for n=2, 3, 4 => output is driven to all lows,
All select lines low for n>4 => output is impredictible (tristate off followed by an inverter),
More than one select line high for n=2, 3, 4 => output is the bitwise OR of selected inputs,
More than one select line high for n>4 => output is impredictible (conflicting drivers, static current).
Encoded muxes have a select line with enough bits to encode the number of inputs. If the value on the select line is i, with 0 d i < n, then the i-th data input is selected. Providing a value higher than n (typically i=4 on a 3-input mux) has similar consequences as setting all select lines to low on a decoded mux.
Think of encoded muxes as decoded muxes with a decoder attached on the select line. The decoder obviously takes up space and time, and whenever possible, a decoded mux should be used. Exceptions for n=2, 3, 4 in the 1-bit version: the implementation combines the decoder and the mux in two levels of nands.
There exists an ambiguity for 2-input muxes: since one bit is enough to select among two inputs, is the select line an atomic wire or a composite wire with only one element? It depends. The rule is that if you use explicitely the 2-input icon, then for convenience it is an atomic wire; if you use the generic icon and set n𡤂, then it is a composite wire with one element. This allows parametrized schematics to use muxes with any number of inputs without making a special case for n=2.
Inverting multiplexers for 2 inputs are provided (same icon as the explicit 2-input mux, but with an inverting dot on the output). They are both smaller and faster than the non-inverting one, but provide an output drive limited to 1/2.
Decoder[a, s]
A decoder inputs an a-bit Address and outputs an s-bit Select. If s is not specified, the default is s=2a. If specified, s must be in (0..2a], One version uses an enable line which, when low, forces Select to all lows.
[ Artwork node; type 'ArtworkInterpress on' to command tool]
The decoders, with special cases for small sizes
Select expresses in unary what the address expresses in binary. The address inverters will soon be replaced by buffers of appropriate size (*).
Decoders with no enable are smaller and faster than decoders with enable.
Counter
Logic provides two types of counters: up-only and up-down.
[Artwork node; type 'ArtworkInterpress on' to command tool]
The counters
In both counters, the Load command overrides the Count or Up/Down commands. The carry/borrow inputs condition the command (Cin for Count or Up, Bin for Down) and the corresponding carry/borrow outputs. In normal usage, they should all be tied up to Vdd. The carry (resp borrow) output is high when the current value of the counter is all 1's (resp all 0's) and the carry (resp borrow) input is high. In the up/down counter, the counter value will remain unchanged if both Up and Down are asserted simultaneously.
The counters use a carry lookahead scheme (a binary tree). They are fairly large, and not very fast. Current Mint estimates for a 32-bit counter are slightly above 25 ns. The implementation may still be improved... The critical path is internal to the counter(s). The command signals are very far down the critical path, and thus may be asserted quite late.
The input load is 1 on the data inputs, 1 or 2 on the control inputs (according to counter size). The drive for the outputs is 1/2 due to internal use of the register output.
ShiftReg
The only shift register provided is left-only. The Load command overrides the Shift command. The input load is 1 on the data input, 1 to 3 on the controls according to the shift register size. The output drive is 1/2 on the direct output (internal use) and 1 on the inverted output.
[Artwork node; type 'ArtworkInterpress on' to command tool]
The left shift-register icon, the shifter cell and control block
The buffers' size is proportional to the shift-register length (*).
4. Standard generators
Generalities
Standard generators are needed for such things as RAMs, for which a standard cell implementation would be disastrous. The standard generator produces a block which can be assembled with other blocks (e.g. standard cells blocks, custom blocks, pads, ...).
Dual-ported Static RAM
The 2-ported RAM has been designed to provide a reasonably dense layout but also a very simple timing. The read and write ports are totally independent. Since nobody needed a precharge, all operations are totally static.
The RAM generator accepts three parameters:
n: the number of words (n must be even)
b: the number of bits
sameSide: a boolean, defaulted to FALSE
If sameSide=TRUE, then all signals appear on the bottom. If sameSide=FALSE, the default value, then the input appears on top and the output on the bottom. The following formulas (known as JMF's first theorem) give the size of the RAM ... until someone squeezes the cells and forgets to update them:
b: bits per word
n: number of words
p: number of address bits (2p<=n<2p+1)
X size (l): p*16+141+b*34+141+p*16 = 32*p+34*b+282
Y size (l): 110+n*52+110 = 52*n+220
The timings are measured from Thyme simulations on a 128 by 128 bits RAM and use a typical model. These times decrease quite linearly as a function of the number of lines. The load on address lines and input data is equivalent to a standard cell load; the drive in output is equivalent to a standard cell drive. The load on enW is n/2 standard cell loads, so using a buffer of size sqrt[n/2] is advised.
Read: address to word line takes 10ns, and word line to output takes at most 20ns, so the data is valid 30ns after the address. When an invalid address is asserted, no word line is high and the output drifts to a low value in about 20ns.
Write: The write cycle uses a positive enable write (enW) signal which must be asserted only when the write address is stable. Since it takes about 5ns to amplify the address, and 3ns to amplify enW through an external buffer, the address should overlap the enW by at least 5ns. The input data should be stable at least 5ns before the end of enW. Finally enW must be asserted for at least 10ns.
Application: a two-cycle write. Let's assume a system clock CK. The write address, the data in, and a "write" signal are clocked by CK. The enW is generated by clocking "write" by a flop whose clock is ~CK; the inverted output NQ is amplified by a buffer of size sqrt[n/2]. As long as the half-cycle is long enough (e.g. at least 10ns), the proper relationship between the write address, data, and enW is garanteed.
[Artwork node; type 'ArtworkInterpress on' to command tool]
Application schematics for a two-cycle write
Fifo - OBSOLETE
The FIFO is made up of two parts: a fifo control block, standard block made of standard cells, and a dual-ported ram (*).
Reset has precedence over Load and UnLoad. Full means n-1 words in the fifo. NF (nearly full) means that there are nbFreeNF words left before the fifo is full. DataAv means the fifo is not empty.
Layout: a mixture of standard cells (counter) and generator (dual-ported RAM).
5. Table of loads and drives
Disclaimer
As long as the library is evolving, it is pretty hard to keep this table accurate. Also, if you rely on this information to compute longest path, you are painfully emulating what Mint does pretty fast, so just use Mint. The load is specified in inverter equivalent (n=24, p=50), and is roughly equal to 0.18pF. The drive is again in inverter equivalent and is a worst case: in the nand4, there are 4 series n-transistors but only parallel p-transistors, and the drive is counted as 1/4. For parametrized macros, only the worst case is shown.
Simple gates
Name drive load
inv 1 1
invBuffer 2 2
tstDriver 2/3 2 (input), 2/3 (NEN), 1/3 (EN)
3BufferI 2/3 2 (input), 1.3 (EN)
3BufferNI 2/3 1 (input), 1.3 (EN)
nand2, nor2 1/2 1
nand3, nor3 1/3 1
nand4, nor4 1/4 1
and2, or2 1 1
and3, or3 1 1
and4, or4 1 1
xor2, xnor2 1/2 2
a22o2i, o22a2i 1/2 1
a21o2i 1/2 1
ff 1 1 (D), 1/3 (CK), 1 (NQ)
ffR 1 1 (D), 1/3 (CK), 1 (r), 1 (Q)
ffP 1 1 (D), 1/3 (CK), 1 (p), 1 (Q)
ffRP 1 1 (D), 1/3 (CK), 1 (r), 1 (p), 1 (Q)
ffEn 1 1 (D), 1/3 (CK), 1 (en), 1 (nEn), 1 (NQ)
reg1 1 1 (D), 1/3 (CK), 1.3 (en), 1 (NQ)
reg1R 1 1 (D), 1/3 (CK), 2 (en), 1 (r), 1 (NQ), 1 (Q)
dLatch 1 1 (D), 1.3 (S)
Macros
Name drive load
invBuffer[d] d d
register[b] 1 1 (Input), b/3 (CK), 2 (en), 1 (nOutput)
registerR[b] 1 2 (Input), b/3 (CK), 2 (en), 1 (output), 1 (nOutput)
registerSimple[b] 1 1 (Input), b/3 (CK), 1 (nOutput)
adder[b] 1/4 (S), 1/3 (COut) 4 (A), 4 (B), 4 (Cin)
comparator[b] 1 2 (A), 2 (B)
eqConstant[b, 0] 1/4 1
eqConstant[b, FF] 1 1
eqConstant[b, v] 1/2 1
3BufferP[b] 2/3 2 (input), 2 (en)
3Buffer[b] 2/3 2 (input), 2 (en)
decoderS[a, s] 1/4 2 (Address)
decoder[a, s] 1/4 2 (Address), 2 (Enable)
muxD21 1 1
muxDN1[3] 1/3 1
muxD41 1/2 1
muxDN1[n>4] 1 2 (In), 1.3 (Select)
mux21 1 1 (In), 2 (Select)
muxN1[3] 1/3 1 (In), 2 (Select)
mux41 1/4 1 (In), 2 (Select)
muxN1[n>4] 1 2 (In), 2 (Select)
muxD2[b] 1 1 (In), 2 (Select)
muxD[3, b] 1/3 1 (In), 3 (Select)
muxD4[b] 1/2 1 (In), 2*b (Select)
muxD[n, b] 1 2 (In), 2.6*b (Select)
mux2[b] 1 1 (In), 2 (Select)
mux[3, b] 1/3 1 (In), 2 (Select)
mux4[b] 1/2 1 (In), 2 (Select)
mux[n, b] 1 2 (In), 2 (Select)
invMux2 1/2 2 (Select), 1 (In0), 1 (In1)
invMux2b[b] 1/2 2 (Select), 1 (In0), 1 (In1)