<> <> <> <> <> <> <<>> <> <> <<>> DIRECTORY CD, Core, CoreCreate, CoreFlat, RosemaryUser, Ports; Logic: CEDAR DEFINITIONS = BEGIN OPEN CoreCreate; <> logicCutSet, macroCutSet: ROPE; -- used by Rosemary fast, macro, gate, transistor: CoreFlat.CutSet; -- use those for the CutSet property <> <> <> <> <> Inv: PROC [buffered: BOOL _ FALSE] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I", "X">> Tr2: PROC [type: ATOM] RETURNS [ct: CellType]; -- $pd, $pdw, $pu, $puw accepted <<"Vdd", "Gnd", "I", "X">> Rec2V: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I", "X", "Vth">> RecTTL: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I", "X">> Buffer: PROC[d: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I", "X">> CKBuffer: PROC[d, numRows: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I", "X">> TstDriver: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I", "X", "EN", "NEN">> TristateI: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I", "X", "EN">> TristateNI: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I", "X", "EN">> <<>> And: PROC[n: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["I", n] "X">> Nand: PROC[n: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["I", n] "X">> Or: PROC[n: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["I", n] "X">> Nor: PROC[n: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["I", n] "X">> Xor2: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I-A", "I-B", "X">> Xnor2: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I-A", "I-B", "X">> <<>> A22o2i: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "A", "B", "C", "D" ,"X">> O22a2i: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "A", "B", "C", "D" ,"X">> A21o2i: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "A", "B", "C" ,"X">> O21a2i: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "A", "B", "C" ,"X">> <<>> Driver: PROC [d: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I", "X">> InvDriver: PROC [d: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I", "nX">> SymDriver: PROC [d: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "I", "X", "nX">> <<>> FlipFlop: PROC [metaStableResistant: BOOL _ FALSE] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "D", "Q", "NQ", "CK">> FlipFlopEnable: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "D", "Q", "NQ", "CK", "en", "nEn">> FlipFlopAsyncReset: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "D", "Q", "NQ", "CK", "r">> DLatch: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "D", "Q", "S">> <> Storage: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "bit", "nbit">> RS: PROC RETURNS [ct: CellType]; <<"Vdd", "Gnd", "R", "S", "Q", "nQ">> <> MuxDN1: PROC [n: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Select", n], Seq["In", n], "Output">> MuxD: PROC [n, b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Select", n], Seq["In", n, Seq[size: b]], Seq["Output", b]>> MuxD2: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "Select0", "Select1", Seq["In0", b], Seq["In1", b], Seq["Output", b]>> MuxD4: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "Select0", "Select1", "Select2", "Select3", Seq["In0", b], Seq["In1", b], Seq["In2", b], Seq["In3", b], Seq["Output", b]>> MuxN1: PROC [n: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Select", s], Seq["In", n], "Output", with s=NbBits[n]>> Mux: PROC [n, b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Select", s], Seq["In", n, Seq[size: b]], Seq["Output", b]>> <> Mux2: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "Select", Seq["In0", b], Seq["In1", b], Seq["Output", b]>> Mux4: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Select", 2], Seq["In0", b], Seq["In1", b], Seq["In2", b], Seq["In3", b], Seq["Output", b]>> InvMux: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "Select", Seq["In0", b], Seq["In1", b], Seq["nOut", b]>> <> TristateBuffer : PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Input", b], Seq["Output", b], "enable">> TristateBufferInv : PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Input", b], Seq["Output", b], "enable">> <> Adder: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "carryIn", Seq["A", b], Seq["B", b], Seq["Sum", b], "carryOut">> Constant: PROC [b: NAT, v: INT] RETURNS [ct: CellType]; <

> Comparator: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["A", b], Seq["B", b], "AEqB">> EqConstant: PROC [b: NAT, v: INT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["In", b], "out">> DecoderS: PROC [a: NAT, s: NAT _ 0] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Address", a], Seq["Select", s], with s=0 => s _ 2**a>> Decoder: PROC [a: NAT, s: NAT _ 0] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Address", a], Seq["Select", s], "Enable", with s=0 => s _ 2**a>> <> Register: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b], Seq["nOutput", b], "en">> RegisterR: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b], Seq["nOutput", b], "en", "r">> RegisterSimple: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b], Seq["nOutput", b]>> CounterCLG: PROC [n: NAT] RETURNS [ct: CellType]; <> <> CounterUp: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "Load", "Count", "Cin", "Cout", "CK", Seq["Input", b], Seq["Output", b], Seq["nOutput", b].>> <> CounterUpDown: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "Load", "Up", "Down", "Cin", "Cout", "Bin", "Bout", "CK", Seq["Input", b], Seq["Output", b], Seq["nOutput", b] (Bin, Bout are the borrow signals).>> <> Latch: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b]>> <> ReverseBits: PROC [b: NAT] RETURNS [public: Core.Wires]; <> Transpose: PROC [b, w: NAT] RETURNS [public: Core.Wires]; <> <<"wSide" has w words of b bits, "bSide" has b words of w bits>> Interleave: PROC [b: NAT] RETURNS [public: Core.Wires]; <> <<"Even[b]", "Odd[b]", "Result[2*b]" Result[2*i]=Even[i], Result[2*i+1]=Odd[i]>> <> Ram2: PROC [b, n: NAT, sameSide, short: BOOL _ FALSE] RETURNS [ct: CellType]; <<"Vdd", "Gnd", Seq["Input", b], Seq["Output", b], Seq["RAdr", a], Seq["WAdr", a], "enW">> <> <<"Vdd", "Gnd", "CK", Seq["Input", b], Seq["Output", b], "Load", "UnLoad", "Reset", "DataAv", "Full", "NF">> <> <> Oracle: PROC [in, out, name: ROPE, log: BOOL _ FALSE] RETURNS [ct: CellType]; <<"In", "Out", "CK">> <> <<-- see in Ports>> SetOracleFileName: PROC [id, fileName: ROPE]; GetOracleFileName: PROC [id: ROPE] RETURNS [fileName: ROPE]; WaveForm: PROC [val: ROPE, freq: NAT, firstEdge: INT] RETURNS [ct: CellType]; <<"RosemaryLogicTime", "Out">> <> ClockGen: PROC [up, dn, firstEdge: INT, initLow: BOOL] RETURNS [ct: CellType]; <<"RosemaryLogicTime", "Clock">> <> Stop: PROC [] RETURNS [ct: CellType]; <> PullUp: PROC [n: NAT] RETURNS [ct: CellType]; RunRosemary: PROC [cellType: CellType, design: CD.Design, cutSet: CoreFlat.CutSet _ NIL] RETURNS [tester: RosemaryUser.Tester]; <> <<$Fast => macro level, $Transistors=transistor level, otherwise gate level.>> <> Counter: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "s0", "s1", "Cin", "Cout", "CK", Seq["Input", b], Seq["Output", b]>> < count down>> < count up>> < idle>> < load input>> ShiftReg: PROC [b: NAT] RETURNS [ct: CellType]; <<"Vdd", "Gnd", "s0", "s1", "CK", "inL", "inR", Seq["Input", b], Seq["Output", b]>> < shift right>> < shift left>> < idle>> < load input>> END.