<> <> <<>> DAUser Install PWCoreLichen <<>> <<-- the first ram, both ports on the same side>> _ &ct _ Logic.Ram2[7, 4, TRUE] _ &ob _ PWCore.Layout[&ct] _ PWCoreLichen.CompareForTheRestOfUs[&ct, LogicMemImpl.ramDesign] _ PW.Draw[&ob] <<-- Please do a drc by hand>> << >> <<-- the first ram, flow-through>> _ &ct _ Logic.Ram2[7, 4, FALSE] _ &ob _ PWCore.Layout[&ct] _ PWCoreLichen.CompareForTheRestOfUs[&ct, LogicMemImpl.ramDesign] _ PW.Draw[&ob] <<-- Please do a drc by hand>> <<>> <<-- the short ram, same side>> _ &ct _ Logic.Ram2[8, 4, TRUE, TRUE] _ &ob _ PWCore.Layout[&ct] _ PWCoreLichen.CompareForTheRestOfUs[&ct, LogicMemImpl.ramShortDesign] _ PW.Draw[&ob] <<-- Please do a drc by hand>> <<-- the short ram, flow-through>> _ &ct _ Logic.Ram2[8, 4, FALSE, TRUE] _ &ob _ PWCore.Layout[&ct] _ PWCoreLichen.CompareForTheRestOfUs[&ct, LogicMemImpl.ramShortDesign] _ PW.Draw[&ob] <<-- Please do a drc by hand>> <<>> <<-- Connectivity Checker: takes forever; BS will take a look (LMM, April 8, 1988)>> <> <<_ &ct _ Logic.Ram2[32, 32, FALSE]>> <<_ &ob _ PWCore.Layout[&ct]>> <<_ CoreOps.SetCellTypeName[&ct, "Ram2Test"]>> <<_ PWCore.Store[&ct, TRUE]>> <> <<_ PW.Draw[&ob]>> <<-- Please do a drc by hand>> <<>> <<-- large test>> <> <> <<_ &design _ CDViewer.FindDesign["LogicRam2"]>> <<_ &cx _ Sisyph.Create[&design, NIL]>> <<_ Sisyph.Store[&cx, "n", NEW[INT _ 128]]>> <<_ Sisyph.Store[&cx, "b", NEW[INT _ 128]]>> <<>> <<-- both ports on the same side>> <<_ &ct _ Sisyph.ES["BothSidesRam.sch", &cx]>> <<_ &ob _ PWCore.Layout[&ct]>> <<_ PW.Draw[&ob]>> <<_ PWCoreLichen.CompareForTheRestOfUs[&ct, &design]>> <<-- Please do a drc by hand>>