CheckLogicRam2.cm
Louis Monier April 28, 1988 9:21:04 pm PDT
DAUser
Install PWCoreLichen
-- the first ram, both ports on the same side
← &ct ← Logic.Ram2[7, 4, TRUE]
← &ob ← PWCore.Layout[&ct]
← PWCoreLichen.CompareForTheRestOfUs[&ct, LogicMemImpl.ramDesign]
← PW.Draw[&ob]
-- Please do a drc by hand
-- the first ram, flow-through
← &ct ← Logic.Ram2[7, 4, FALSE]
← &ob ← PWCore.Layout[&ct]
← PWCoreLichen.CompareForTheRestOfUs[&ct, LogicMemImpl.ramDesign]
← PW.Draw[&ob]
-- Please do a drc by hand
-- the short ram, same side
← &ct ← Logic.Ram2[8, 4, TRUE, TRUE]
← &ob ← PWCore.Layout[&ct]
← PWCoreLichen.CompareForTheRestOfUs[&ct, LogicMemImpl.ramShortDesign]
← PW.Draw[&ob]
-- Please do a drc by hand
-- the short ram, flow-through
← &ct ← Logic.Ram2[8, 4, FALSE, TRUE]
← &ob ← PWCore.Layout[&ct]
← PWCoreLichen.CompareForTheRestOfUs[&ct, LogicMemImpl.ramShortDesign]
← PW.Draw[&ob]
-- Please do a drc by hand
-- Connectivity Checker: takes forever; BS will take a look (LMM, April 8, 1988)
Install ConnectivityChecker
← &ct ← Logic.Ram2[32, 32, FALSE]
← &ob ← PWCore.Layout[&ct]
← CoreOps.SetCellTypeName[&ct, "Ram2Test"]
← PWCore.Store[&ct, TRUE]
CheckConnectivity Ram2TestLayout.dale
← PW.Draw[&ob]
-- Please do a drc by hand
-- large test
cdread LogicRam2
Statistics on
← &design ← CDViewer.FindDesign["LogicRam2"]
← &cx ← Sisyph.Create[&design, NIL]
← Sisyph.Store[&cx, "n", NEW[INT ← 128]]
← Sisyph.Store[&cx, "b", NEW[INT ← 128]]
-- both ports on the same side
← &ct ← Sisyph.ES["BothSidesRam.sch", &cx]
← &ob ← PWCore.Layout[&ct]
← PW.Draw[&ob]
← PWCoreLichen.CompareForTheRestOfUs[&ct, &design]
-- Please do a drc by hand