DIRECTORY CD, Connections, Rope, Route; Cabbage: CEDAR DEFINITIONS = BEGIN Error: ERROR [errorType: ErrorType _ callingError, explanation: Rope.ROPE _ NIL]; Signal: SIGNAL [errorType: ErrorType _ callingError, explanation: Rope.ROPE _ NIL]; ErrorType: TYPE = {programmingError, callingError, noResource, designRuleViolation, other}; PadRingParams: TYPE = REF PadRingParamsRec; PadRingParamsRec: TYPE = RECORD [ horizLayer: Rope.ROPE, -- "poly", "metal" or "metal2" vertLayer: Rope.ROPE, -- "poly", "metal" or "metal2" technologyKey: ATOM _ $cmosB, -- $cmosA or $cmosB outerBTChanWidth, outerLRChanWidth: INT _ 32, -- width of channel at periphery in lambdas powerBTCellWidth, powerLRCellWidth: INT _ 200, -- width of power at periphery in lambdas opt: Route.Optimization _ noIncompletes, -- controls runtime vs quality signalSinglePinNets: BOOLEAN _ TRUE -- SIGNAL if there are any single pin nets ]; defaultPadRingParams: PadRingParams; WireWidthProc: TYPE = PROC[netName: Rope.ROPE, context: REF ANY _ NIL] RETURNS [wireWidth: INT]; Center: PROC [inner, bottomLeft, bottom, bottomRight, right, topRight, top, topLeft, left: CD.Object, parms: Cabbage.PadRingParams] RETURNS [innerPos: CD.Position]; PadRoute: PROC [inner, bottomLeft, bottom, bottomRight, right, topRight, top, topLeft, left: CD.Object, innerPos: CD.Position, connections: Connections.Table, parms: PadRingParams _ defaultPadRingParams, name: Rope.ROPE _ NIL] RETURNS [chip: CD.Object]; PadLimitedRoute: PROC [inner, bottomLeft, bottom, bottomRight, right, topRight, top, topLeft, left: CD.Object, innerPos: CD.Position, connections: Connections.Table, parms: PadRingParams _ defaultPadRingParams, name: Rope.ROPE _ NIL] RETURNS [chip: CD.Object]; END. Cabbage.mesa Copyright Ó 1986, 1987 by Xerox Corporation. All rights reserved. Created by Bryan Preas, May 21, 1986 2:59:20 pm PDT Last Edited by: September 24, 1987 4:46:50 pm PDT Bertrand Serlet April 29, 1987 5:35:11 pm PDT Theory This interface allows easy routing of interior of chips to pad frames. Interconnection requirements are specified by the Connections interface. The input objects are the interior of the chip, the four sides of the chip containing the pads, and the four corners of the pad frame. Signal connections to the corners are not allowed. Routing is performed in two modes: normal and pad limited. Normal routing is performed in eight areas: four channels whose length are defined by the dimensions of the interior object, and four switchboxes in the corners. Pins on the bonding pad sides are not allowed to cross the "seams" among the routing areas. Pad limited routing is performed in four areas: two channels whose length are defined by the dimensions of the interior object, and two switchboxes on the upper and lower surfaces. Pins on the bonding pad sides are not allowed to cross the "seams" among the routing areas. Nets with the names "Vdd" and "Gnd" are distinguished. The are not permitted to participate in constraint loops with each other. Pins of these nets on the side surfaces the conflict with pins of the other net are not included in the routing. Restrictions: 1. Currently wire widths specifications from Connections are transformed to net names. This means that there can be only one wire width per net name. 2. Incomplete routing may occur if the switchbox areas (the corners) are too small or too congested in a part of the switchbox. Automatic recovery is planned but not implemented. 3. The portions of the left and right bonding pad sides that are routed with switchboxes can have only one net per portion. Also, these portions must have "sparse" connections: spacing should be much greater than the minimum pin-to-pin spacing . Errors Types -- All the parameters for the channel and switchbox router The pad router will signal if design rule violations are found in the input. Proceeding from the signals may cause design rule violations in the routing!! Setting the Signal Booleans to FALSE should be used with caution!! width of the trunk for a specified net Preparing the input Returns the innerPos needed for centering the inner in the pad frame. This is usually what is desired. However the position of the inner cell can be positioned other than in the center. Refer to discussion of PadRoute. Route the chip Two procedured are supplied: PadRoute and PadLimitedRoute. PadRoute will work for all chips but sometimes does not exploit the area in the corners of pad limited chips well. PadLimitedRoute divides the routing areas differently to route pad limited chips better. inner is the interior part of the chip bottomLeft, bottom, bottomRight, right, topRight, top, topLeft, left are the objects in the pad ring; any may be NIL. Dimensions of the corner objects should not be smaller than the projections of their adjacent sides. The pad ring objects are "glued" together with wiring for those connections that are compatabel at the boundries. innerPos must place the inner object in the interior of the padring; otherwise it is ignored. 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