
<<CabbageTest.mesa>>
<<Copyright Ó 1986, 1987 by Xerox Corporation.  All rights reversed.>>
    <<Bryan Preas May 22, 1986 12:25:02 pm PDT>>
    <<Bertrand Serlet April 27, 1987 0:47:15 am PDT>>

<<Use with the file CabbageTest.dale to test routing:>>
<<CabbageTest.cm>>

DIRECTORY 
Cabbage, CD, Connections, PW, PWPins, Rope;

CabbageTest: CEDAR PROGRAM    
IMPORTS Cabbage, Connections, PW, PWPins =
 BEGIN 

TestBasicCabbage: PW.GeneratorProc =
BEGIN
routerParams: Cabbage.PadRingParams _ NEW[Cabbage.PadRingParamsRec _ [horizLayer: "metal2", vertLayer: "metal", technologyKey: 
design.technology.key, outerBTChanWidth: 32, powerBTCellWidth: 60, outerLRChanWidth: 32, powerLRCellWidth: 60]];

left: CD.Object _ PW.Get[design, "BasicLeft"];
right: CD.Object _ PW.Get[design, "BasicRight"];
top: CD.Object _ PW.Get[design, "BasicTop"];
bottom: CD.Object _ PW.Get[design, "BasicBottom"];
inner: CD.Object _ PW.Get[design, "BasicInner"];
innerPos: CD.Position _ Cabbage.Center[inner, NIL, bottom, NIL, right, NIL, top, NIL, left, routerParams];
connections: Connections.Table _ GetConnections[inner, bottom, right, top, left];
test: CD.Object _ Cabbage.PadRoute[inner, NIL, bottom, NIL, right, NIL, top, NIL, left, innerPos, connections, routerParams];
RETURN[test];
END;

TestPadLimited: PW.GeneratorProc =
BEGIN
routerParams: Cabbage.PadRingParams _ NEW[Cabbage.PadRingParamsRec _ [horizLayer: "metal2", vertLayer: "metal", technologyKey: 
design.technology.key, outerBTChanWidth: 24, powerBTCellWidth: 60, outerLRChanWidth: 32, powerLRCellWidth: 22]];

left: CD.Object _ PW.Get[design, "PinLimitedLeft"];
right: CD.Object _ PW.Get[design, "PinLimitedRight"];
top: CD.Object _ PW.Get[design, "PinLimitedTop"];
bottom: CD.Object _ PW.Get[design, "PinLimitedBottom"];
inner: CD.Object _ PW.Get[design, "PinLimitedInner"];
innerPos: CD.Position _ Cabbage.Center[inner, NIL, bottom, NIL, right, NIL, top, NIL, left, routerParams];
connections: Connections.Table _ GetConnections[inner, bottom, right, top, left];
test: CD.Object _ Cabbage.PadLimitedRoute[inner, NIL, bottom, NIL, right, NIL, top, NIL, left, innerPos, connections, routerParams];
RETURN[test];
END;

TestPowerPL: PW.GeneratorProc =
BEGIN
routerParams: Cabbage.PadRingParams _ NEW[Cabbage.PadRingParamsRec _ [horizLayer: "metal2", vertLayer: "metal", technologyKey: 
design.technology.key, outerBTChanWidth: 32, powerBTCellWidth: 75, outerLRChanWidth: 32, powerLRCellWidth: 60]];

left: CD.Object _ PW.Get[design, "PowerPLLeft"];
right: CD.Object _ PW.Get[design, "PowerPLRight"];
top: CD.Object _ PW.Get[design, "PowerPLTop"];
bottom: CD.Object _ PW.Get[design, "PowerPLBottom"];
inner: CD.Object _ PW.Get[design, "PowerPLInner"];
innerPos: CD.Position _ Cabbage.Center[inner, NIL, bottom, NIL, right, NIL, top, NIL, left, routerParams];
connections: Connections.Table _ GetConnections[inner, bottom, right, top, left];
test: CD.Object _ Cabbage.PadLimitedRoute[inner, NIL, bottom, NIL, right, NIL, top, NIL, left, innerPos, connections, routerParams];
RETURN[test];
END;

    GetConnections: PROC [inner, bottom, right, top, left: CD.Object] RETURNS [connections: Connections.Table] ~ {
        UseAll: Connections.PinFilterProc ~ {keepIt _ TRUE};
        UseTop: Connections.PinFilterProc ~ {keepIt _ PWPins.GetSide[obj, inst].side=top};
        UseLeft: Connections.PinFilterProc ~ {keepIt _ PWPins.GetSide[obj, inst].side=left};
        UseBottom: Connections.PinFilterProc ~ {keepIt _ PWPins.GetSide[obj, inst].side=bottom};
        UseRight: Connections.PinFilterProc ~ {keepIt _ PWPins.GetSide[obj, inst].side=right};

        connections _ Connections.CreateForRopes[];
        Connections.InsertPins[connections, inner, UseAll];
        Connections.InsertPins[connections, bottom, UseTop];
        Connections.InsertPins[connections, right, UseLeft];
        Connections.InsertPins[connections, top, UseBottom];
        Connections.InsertPins[connections, left, UseRight];
        };

PW.RegisterGenerator[TestBasicCabbage, "TestBasicCabbage"];
PW.RegisterGenerator[TestPadLimited, "TestPadLimited"];
PW.RegisterGenerator[TestPowerPL, "TestPowerPL"];
END.