<> <> <> <> DIRECTORY Boole, BooleCore, Core, CoreCreate, CoreOps, PW, PWCore; MeadConwayPLA: CEDAR PROGRAM IMPORTS Boole, BooleCore, CoreCreate, CoreOps, PW, PWCore = BEGIN OPEN Boole; Create: PROC RETURNS [cellType: Core.CellType] = { inputs: BooleCore.Inputs _ NIL; outputs: BooleCore.Outputs _ NIL; wa: Core.Wire = CoreOps.CreateWire[name: "A"]; wb: Core.Wire = CoreOps.CreateWire[name: "B"]; wc: Core.Wire = CoreOps.CreateWire[name: "C"]; inv: Core.CellType _ BooleCore.GetCellLibraryCell["InputDriver"]; out: Core.CellType _ BooleCore.GetCellLibraryCell["OutputDriver"]; pas: LIST OF CoreCreate.PA _ LIST[["VRef", "VRef"]]; inputs _ CONS [[input: "A", driver: inv], inputs]; inputs _ CONS [[input: "B", driver: inv], inputs]; inputs _ CONS [[input: "C", driver: inv], inputs]; outputs _ CONS [[output: "Z1", driver: out, expr: wa, pas: pas], outputs]; outputs _ CONS [[output: "Z2", driver: out, expr: Or[wa, And[Not[wa], Not[wb], wc]], pas: pas], outputs]; outputs _ CONS [[output: "Z3", driver: out, expr: And[Not[wb], Not[wc]], pas: pas], outputs]; outputs _ CONS [[output: "Z4", driver: out, expr: Or[And[Not[wa], Not[wb], wc], And[Not[wa], wb, Not[wc]]], pas: pas], outputs]; <<-- Generate the block Alps>> cellType _ BooleCore.AlpsCell[ name: "MeadConwayPLA", public: CoreCreate.Wires[wa, wb, wc, "Z1", "Z2", "Z3", "Z4", "Vdd", "Gnd", "VRef"], inputs: inputs, outputs: outputs ]; }; MakeMeadConwayPLA: PW.GeneratorProc = {RETURN [PWCore.Layout[Create[]]]}; PW.RegisterGenerator[MakeMeadConwayPLA, "MakeMeadConwayPLA"]; END.