Abstract: Boole (also called Alps) is a layout generator which accepts a set of boolean equations, much like PLA generators do. It makes use of an original tree-structured representation of arbitrary boolean expressions. This representation is usually more compact than the classic disjunctive form, is suitable for fast symbolic manipulation, and maps naturally into silicon. Boole produces static CMOS layout using the cascode switch style. In the same package, there is a starting point for finite state machines.

Created by: Bertrand Serlet

Maintained by: Bertrand Serlet <Serlet.pa>

Keywords: Boolean Algebra, Boolean expressions, Disjunctive Normal Form, PLA, DCVS, Cascode, Static, FSM, Finite State Machines, Automatas