LAYOUT GENERATION THROUGH PARAMETERIZED SCHEMATICS
Louis Monier
Xerox PARC
Computer Science Laboratory
3333 Coyote Hill Road
Palo Alto, CA 94304, USA
We illustrate through examples a DA system developed and used at PARC. The main idea is to capture a design through a mixture of parameterized schematics and code. Some of the parameters are annotations to drive layout generation. The system leads to concise and legible circuit descriptions, and freely mixes all styles of layout.